Sram cell structure with 3 p-channel transistors and 3 n-channel transistors and method of operating the sram cell

A method of operating a SRAM cell structure comprising a first inverter composed of a CMOS, a second inverter composed of a CMOS, a first access transistor composed of an N-channel transistor and connected between a bit line (BL) and the input terminal of the first inverter, and a second access transistor composed of a P-channel transistor and connected in parallel with the first access transistor, the method comprising the following steps for a read operation:

• (a1) precharging the bit line (BL) with a first voltage corresponding to signal ‘1’ and setting a WRITE signal (WWL) to ‘0’;
• (a2) applying the voltage corresponding to the signal ‘1’ to a word line (WL) connected to a gate electrode of the first access transistor to turn on the first access transistor;
• (a3) applying a voltage corresponding to the inverse signal (WWL) of the WRITE signal (WWL=0) to a gate electrode of the second access transistor to turn off the second access transistor;
• (a4) sensing a second voltage of the bit line after a preset time has elapsed from the state in which the first access transistor is turned on and the second access transistor is turned off;
• (a5) detecting a difference between the first voltage and the second voltage of the bit line;
• and
• (a6) determining the stored data of the SRAM cell according to the detected difference of the bit line.