Static random access memory and its layout pattern

A layout pattern of static random access memory (SRAM), at least comprising:

• a substrate;
• a plurality of fin structures positioned on the substrate;
• a plurality of gate structures located on the substrate and span the plurality of fin structures to form a plurality of transistors distributed on the substrate, wherein each transistor includes a part of the gate structure spans a part of the fin structure, wherein the transistors include:
• a first pull-up transistor (PU1), a first pull-down transistor (PD1), a second pull-up transistor (PU2) and a second pull-down transistor (PD2) form a latch circuit;
• a first access transistor (PG1) and a second access transistor (PG2) connected to the latch circuit;
• and
• a first read port transistor (RPD) and a second read port transistor (RPG) connected in series, wherein the gate structure of the first read port transistor (RPD) is connected to the gate structure of the first pull-down transistor (PD1), and wherein the first pull-down transistor (PD1) is disposed between the first pull-up transistor (PU1) and the first read port transistor (RPD);
• wherein a drain of the first pull-down transistor (PD1) is connected to a first voltage source Vss1, and a drain of the first read port transistor (RPD) is connected to a second voltage source Vss2, wherein the gate of the first read port transistor (RPD) directly contacts the gate of the first pull-up transistor (PU1) and the gate of the first pull-down transistor (PD1), wherein the first voltage source Vss1 is connected to a first metal layer, and the second voltage source Vss2 is connected to a second metal layer, wherein the first metal layer is not in direct contact with the second metal layer.