Image sensor and electronic device including the same

An image sensor comprising:

• a pixel array including a plurality of pixels arranged in a first direction and in a second direction, the second direction intersecting the first direction;
• and
• a logic circuit configured to:
• generate first image data having a first resolution based on the plurality of pixels;
• generate a plurality of second image data having a second resolution based on a plurality of binning pixels;
• generate third image data having the first resolution based on the plurality of pixels;
• output the first image data;
• output the plurality of second image data after outputting the first image data;
• and
• output the third image data after outputting the plurality of second image data,
• wherein a first frames per second of the first image data is lower than a second frames per second of the plurality of second image data,
• wherein the second resolution is lower than the first resolution,
• wherein a first time period at which the first image data is output and a second time period at which the plurality of second image data is output are alternately repeated, and
• wherein the logic circuit is further configured to output one image frame between the first time period and the second time period, alternately repeated, the one image frame having the second resolution.

An image sensor comprising:

• a pixel array including a plurality of pixels arranged in a first direction and in a second direction, the second direction intersecting the first direction;
• and
• a logic circuit configured to:
• generate first image data having a first resolution based on the plurality of pixels;
• and
• generate a plurality of second image data having a second resolution based on a plurality of binning pixels;
• wherein the second resolution is lower than the first resolution,
• wherein the first image data is RGB data and the plurality of second image data is black and white image data,
• wherein a first time period at which the first image data is output and a second time period at which the plurality of second image data is output are alternately repeated, and
• wherein the logic circuit is further configured to output one image frame between the first time period and the second time period, alternately repeated, the one image frame having the second resolution.