Memory, memory module, memory system, and operation method of memory system
AssigneeSK hynix Inc.
InventorSeok Woo Choi
Life of this patent
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Abstract
A memory system may include an error correction code generation circuit configured to generate a first error correction code having a large bit number by using write data and a first H matrix in a first error correction mode, and to generate a second error correction code having a small bit number by using the write data and a second H matrix in a second error correction mode, and a memory core configured to store the first error correction code and the write data in the first error correction mode, and to store the second error correction code and the write data in the second error correction mode.
Claims16
A memory comprising:
- a first parity generation circuit configured to generate a first parity by using write data in respective first and second error correction modes;
- a second parity generation circuit configured to generate a second parity by using the write data in the first error correction mode;
- a first cell array configured to store the write data;
- a second cell array configured to store the first parity;
- and
- a third cell array configured to store the second parity.
A memory module comprising:
- a module controller including:
- a first parity generation circuit configured to generate a first parity by using write data in respective first and second error correction modes;
- and
- a second parity generation circuit configured to generate a second parity by using the write data in the first error correction mode;
- one or more first memories configured to store the write data;
- one or more second memories configured to store the first parity;
- and
- one or more third memories configured to store the second parity.
A memory system comprising:
- a memory controller including:
- a first parity generation circuit configured to generate a first parity by using write data in respective first and second error correction modes;
- and
- a second parity generation circuit configured to generate a second parity by using the write data in the first error correction mode;
- one or more first memories configured to store the write data;
- one or more second memories configured to store the first parity;
- and
- one or more third memories configured to store the second parity.
An operation method of a memory system, the operation method comprising:
- generating a first parity and a second parity corresponding to write data by using the write data to store the write data, the first parity, and the second parity in memory cells selected from a memory core by a write address during a write operation in a first error correction mode;
- reading data and the first parity from memory cells selected from the memory core by a read address to correct an error in the read data by using the read first parity during a read operation in a second error correction mode.
Dependencies are inferred from the claim text.