HD3 cancellation technique in RF DACs and digital transmitters
AssigneeAvago Technologies International Sales Pte. Limited
InventorsMohyee Mikhemar, Alvin Lin Lai, Arya Behzad, Wei-Hong Chen, Ahmed Sayed Hamza
Life of this patent
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Abstract
A transmitter includes a first circuit to generate multiphase pulses, and a second circuit to mix a set of in-phase (I) data and quadrature (Q) data with the multiphase pulses and to generate an output radiofrequency (RF) signal. The multiple pulses include multiple I pulses and multiple Q pulses each comprising a pulse that includes a duty cycle such that a first null appears at a third harmonic frequency in a frequency spectrum of the pulse.
Claims14
An apparatus, comprising:
- a first circuit configured to generate multiphase pulses;
- and
- a second circuit configured to mix a set of in-phase (I) data and quadrature (Q) data with the multiphase pulses,
- wherein:
- the multiphase pulses comprise multiple I pulses and multiple Q pulses each comprising a pulse having a duty cycle,
- wherein the first circuit is configured to generate the multiphase pulses having the duty cycle such that a first null appears at a third harmonic frequency of the pulse, and
- wherein the first circuit comprises a delay locked loop (DLL) configured to selectively produce adjusted duty cycle values of the multiphase pulses to be within 30-35% or within 45-55%.
An integrated circuit, comprising:
- a first circuit configured to generate a set of multiphase pulses with duty cycles;
- and
- a second circuit configured to receive the set of multiphase pulses and reject a third harmonic distortion (HD3) of the set of multiphase pulses, wherein
- the multiphase pulses comprise multiple in-phase (I) pulses and multiple quadrature (Q) pulses each comprising a pulse having a duty cycle, and
- the first circuit comprises a delay locked loop (DLL) configured to selectively produce adjusted duty cycle values of the multiphase pulses to be within 30-35% or within 45-55% to reject the HD3.
A communication device, comprising:
- a first circuit configured to generate a set of four-phase LO pulses;
- and
- a second circuit configured to mix in-phase (I) data and quadrature (Q) data with the set of four-phase LO pulses,
- wherein the first circuit is further configured to generate the set of four-phase LO pulses with duty cycles such that a first null of a frequency spectrum of a pulse of the set of four-phase LO pulses occurs at a third harmonic frequency,
- the four-phase LO pulses comprise multiple I pulses and multiple Q pulses each comprising a pulse having a duty cycle, and
- the first circuit comprises a delay locked loop (DLL) configured to selectively produce adjusted duty cycle values of the four-phase LO pulses to be within 30-35% or within 45-55%.
Dependencies are inferred from the claim text.