Fast calibration of phase lock loops

A calibration method for use in a controller configured to determine a calibrated value of a calibration parameter for a phase lock loop configured to generate a clock signal, the method comprising:

• finding a lower bound by stepping downward from an initial value of the calibration parameter while a frequency error remains below a predetermined threshold;
• finding an upper bound by stepping upward from the initial value while the frequency error remains below the predetermined threshold;
• and
• using a value greater than or equal to the lower bound and less than or equal to the upper bound as the calibrated value,
• wherein the frequency error is determined by:
• subtracting a cycle count of the clock signal in a predetermined time from a predetermined target count to obtain a difference;
• and
• taking an absolute value of the difference.

A non-transient information storage medium coupled to a controller to provide firmware that configures the controller to implement a calibration method to determine a calibrated value of a calibration parameter for a phase lock loop configured to generate a clock signal, the calibration method comprising:

• finding a lower bound by stepping downward from an initial value of the calibration parameter while a frequency error remains below a predetermined threshold;
• finding an upper bound by stepping upward from the initial value while the frequency error remains below the predetermined threshold;
• and
• using a value greater than or equal to the lower bound and less than or equal to the upper bound as the calibrated value,
• wherein if the frequency error exceeds the predetermined threshold for the initial value of the calibration parameter the calibration method further includes:
• performing a bottom-up or top-down search to find the lower bound and the upper bound, wherein a step size for said stepping downward and said stepping upward is at least twice a step size of the bottom-up or top-down search.