Low power consumption power-on reset system

A power-on reset system comprising:

• an SR latch circuit, powered by a supply voltage and configured to generate a power-on reset signal according to the supply voltage and an enable signal, wherein an enablement or a disablement of the enable signal is unrelated to a rising edge or a falling edge of the supply voltage, wherein the enablement of the enable signal includes a first enablement of the enable signal;
• and
• at least one operating circuit, powered by the supply voltage and configured to reset at least one state circuit within each of the at least one operating circuit according to the power-on reset signal;
• wherein when the supply voltage starts up, an output terminal of the SR latch circuit is configured to have and keep at a predetermined state, such that after a start-up of the supply voltage and before the first enablement of the enable signal, the power-on reset signal is in a reset state to reset the at least one state circuit within each of the at least one operating circuit;
• wherein after the first enablement of the enable signal subsequent to the start-up of the supply voltage, the power-on reset signal turns to a non-reset state.