Solid state drive (SSD) with in-flight erasure iteration suspension
AssigneeSK Hynix NAND Product Solutions Corp.
InventorsJustin R. Dayacap, Shantanu R. Rajwade, Kyung Jean Yoon, Ali Khakifirooz, David J. Pelster, Yogesh B. Wakchaure, Xin Guo
Life of this patent
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Abstract
An apparatus is described. The apparatus includes a memory chip having logic circuitry to suspend application of an erasure voltage, wherein, respective responses of the erasure voltage to a decision to suspend the application of the erasure voltage depend on where the erasure voltage is along its waveform.
Claims18
An apparatus, comprising:
- a memory;
- and
- a hardware processor coupled to the memory and configured at least to:
- apply an erase voltage to one or more storage cells;
- while applying the erase voltage to the one or more storage cells:
- receive a command to suspend applying the erase voltage to the one or more storage cells;
- determine that the erase voltage exceeds a critical voltage;
- determine that an amount of time during which the erase voltage exceeds the critical voltage does not meet a first predetermined threshold;
- and
- in response to receiving the command to suspend applying the erase voltage to the one or more storage cells, determining that the erase voltage exceeds the critical voltage, and determining that the amount of time during which the erase voltage exceeds the critical voltage does not meet the first predetermined threshold:
- continue to apply the erase voltage to the one or more storage cells for a first period of time;
- and
- suspend applying the erase voltage to the one or more second storage cells after the first period of time.
A method, comprising:
- applying an erase voltage to one or more storage cells;
- while applying the erase voltage to the one or more storage cells:
- receiving a command to suspend applying the erase voltage to the one or more storage cells;
- determining that the erase voltage exceeds a critical voltage;
- determining that an amount of time during which the erase voltage exceeds the critical voltage does not meet a first predetermined threshold;
- and
- in response to receiving the command to suspend applying the erase voltage to the one or more storage cells, determining that the erase voltage exceeds the critical voltage, and determining that the amount of time during which the erase voltage exceeds the critical voltage does not meet the first predetermined threshold:
- continuing to apply the erase voltage to the one or more storage cells for a first period of time;
- and
- suspending applying the erase voltage to the one or more storage cells after the first period of time.
A non-transitory computer-readable medium containing computer executable instructions that, when executed by a processor, cause the processor to perform a method, the method comprising:
- applying an erase voltage to one or more storage cells;
- and
- while applying the erase voltage to the one or more storage cells:
- receiving a command to suspend applying the erase voltage to the one or more storage cells;
- determining that the erase voltage exceeds a critical voltage;
- determining that an amount of time during which the erase voltage exceeds the critical voltage does not meet a first predetermined threshold;
- and
- in response to receiving the command to suspend applying the erase voltage to the one or more storage cells, determining that the erase voltage exceeds the critical voltage, and determining that the amount of time during which the erase voltage exceeds the critical voltage does not meet the first predetermined threshold:
- continuing to apply the erase voltage to the one or more storage cells for a first period of time;
- and
- suspending applying the erase voltage to the one or more storage cells after the first period of time.
Dependencies are inferred from the claim text.