Multi-ported memory array utilizing bitcells with balanced P-N diffusion layouts

A memory device comprising:

• at least one bitcell coupled to a local bitline, the local bitline comprising a plurality of pre-discharge devices, and the at least one bitcell comprising:
• a first set of a plurality of transistor devices configured to form at least one write port, the at least one write port to receive digital data;
• a second set of the plurality of transistor devices configured as an inverter pair, the inverter pair to store the digital data;
• a third set of the plurality of transistor devices configured to form at least one read port, the at least one read port to access the digital data stored at the inverter pair and output the digital data to a node on the local bitline, and the plurality of transistor devices consisting of an equal number of P-channel transistor devices and N-channel transistor devices, wherein the first set and the third set comprise transistor devices of a different type, at least one of the first set or the third set comprises transistor devices with a common gate terminal, and at least one of the plurality of pre-discharge devices pre-discharges the node to a source supply voltage (Vss);
• and
• read merge circuitry coupled to the local bitline, the read merge circuitry comprising a plurality of pre-discharge devices coupled to a corresponding plurality of clipper devices, and the read merge circuitry to:
• pre-discharge a node of the local bitline at a first read port of the at least one read port of the bitcell to a source supply voltage (Vss) at a first pre-discharge device of the plurality of pre-discharge devices;
• initiate charge sharing between the node of the local bitline and a full swing local bitline node of the read merge circuitry via a first clipper device of the plurality of clipper devices;
• and
• assert a read wordline (RWL) at a read transfer transistor of the bitcell to cause a read operation at the first read port.