Delay adjuster based clock qualifier timing enhancement for memory interface

A memory interface circuit, comprising:

• a first receiver having a first input, a second input, and an output, wherein the first input of the first receiver is configured to receive a first data strobe signal, and the second input of the first receiver is configured to receive a second data strobe signal;
• a second receiver having a first input, a second input, and an output, wherein the first input of the second receiver is configured to receive the second data strobe signal, and the second input of the second receiver is configured to receive a first reference voltage;
• a gating circuit having a first input, a second input, and an output, wherein the first input of the gating circuit is coupled to the output of the first receiver;
• a gate control circuit having a first input, a second input, and an output, wherein the second input of the gate control circuit is coupled to the output of the first receiver, and the output of the gate control circuit is coupled to the second input of the gating circuit;
• a delay adjuster coupled between the output of the second receiver and the first input of the gate control circuit;
• a third receiver having a first input, a second input, and an output, wherein the first input of the third receiver is configured to receive a data signal, and the second input of the third receiver is configured to receive a second reference voltage;
• and
• a data capture circuit having a data input, a clock input, and an output, wherein the data input of the data capture circuit is coupled to the output of the third receiver, and the clock input of the data capture circuit is coupled to the output of the gating circuit.

A method for operating a memory interface circuit, comprising:

• generating an internal data strobe signal based on a first data strobe signal and a second data strobe signal using a first receiver;
• generating a qualifier signal based on the second data strobe signal and a reference voltage using a second receiver;
• delaying a rise time and a fall time of the qualifier signal using a delay adjuster;
• generating a gate control signal based on the internal data strobe signal and the qualifier signal after the delay adjuster;
• and
• gating a portion of the internal data strobe signal based on the gate control signal to provide a read clock signal, wherein generating the gate control signal comprises propagating the gate control signal through a qualifier flip-flop and one or more strobe flip-flops, wherein the qualifier flip-flop is clocked by the qualifier signal after the delay adjuster, and each of the one or more strobe flip-flops is clocked by the internal data strobe signal.