Data storage circuit and control method thereof, and storage apparatus

A method for controlling data storage, applied to a data storage circuit for DRAM, the data storage circuit comprising a sense amplifier array and a first storage array positioned on a side of the sense amplifier array, a main bit line being electrically connected to the sense amplifier array, the first storage array comprising a plurality of first sub storage arrays, each of the plurality of first sub storage arrays comprising a plurality of first sub bit lines and a plurality of first selector switches arranged in one-to-one correspondence, each of the plurality of first sub bit lines being electrically connected to the main bit line via a corresponding one of the plurality of first selector switches, and each of the plurality of first sub bit lines is controlled independently of the other first sub bit lines by the corresponding one of the plurality of first selector switches, wherein each memory cell in the first storage array is configured to be read or written via being electrically connected to a single first sub bit line, a number of the plurality of first sub bit lines in each of the plurality of first sub storage arrays is more than two, and a number of the plurality of first selector switches in each of the plurality of first sub storage arrays is more than two, and wherein the plurality of first sub bit lines are further electrically connected to a preset equalization voltage via a plurality of first equalizer switches, and the plurality of first sub bit lines and the plurality of first equalizer switches are arranged in one-to-one correspondence, the method comprising:

• controlling a given one of the plurality of first selector switches corresponding to a selected one of the plurality of first sub storage arrays to be turned on to electrically connect a corresponding one of the plurality of first sub bit lines and the main bit line, and controlling a given one of the plurality of first selector switches corresponding to an unselected one of the plurality of first sub storage arrays to be turned off;
• and
• controlling the sense amplifier array to be in an amplification stage to amplify a signal of the main bit line, wherein a start moment of the amplification stage is later than a start moment of turn-on of the given first selector switch.