# US 12,620,050 B1 · Decoding acceleration with hardware decoder

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- Number: US 12,620,050 B1
- Document ID: US12620050B1
- Status: Granted
- Kind: B1
- Application number: 17/804,791
- Filed: 2022-05-31
- Granted: 2026-05-05
- Earliest claimed: 2022-05-31
- Assignees: Amazon Technologies, Inc.
- Applicants: Amazon Technologies, Inc.
- Inventors: Xiaodan Tan; Paul Gilbert Meyer
- Web page: https://patentgrep.com/patent/US12620050B1

## CPC

- G06T 1/20: Processor architectures; Processor configuration, e.g. pipelining
- G06T 9/005: {Statistical coding, e.g. Huffman, run length coding}
- H04N 19/42: characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation (H04N19/635 takes precedence)
- H04N 19/436: using parallelised computational arrangements
- H04N 19/44: Decoders specially adapted therefor, e.g. video decoders which are asymmetric with respect to the encoder
- H04N 19/625: using discrete cosine transform [DCT]
- H04N 19/91: Entropy coding, e.g. variable length coding [VLC] or arithmetic coding
- G06T: IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
- H04N: PICTORIAL COMMUNICATION, e.g. TELEVISION

## Abstract

Techniques to speed up decoding of compressed data objects may include offloading a decoding function to a decoder accelerator. The techniques may include a processor parsing the header including one or more code tables from a compressed data object, loading code data for one or more code tables into the decoder accelerator, and providing the encoded data from the compressed data object to the decoder accelerator via a decoder bus interface. The decoder accelerator decodes the encoded data into decoded data blocks. The processor then receives the decoded data blocks from the decoder accelerator via the decoder bus interface, generates pre-transformation data blocks based on the decoded data blocks by performing inverse domain transformation, and converts the pre-transformation data blocks into a decompressed data object.

## Claims

### Claim 1

A computing system to accelerate JPEG (Joint Photographic Experts Group) image decoding, the computing system comprising:
a processor; and
a decoder accelerator coupled to the processor via a decoder bus interface,
wherein the processor is operable to:
parse a JPEG file to obtain a header including one or more quantization tables and a plurality of Huffman code tables;
load the plurality of Huffman code tables into the decoder accelerator via the decoder bus interface;
transmit encoded data in the JPEG file to the decoder accelerator via the decoder bus interface;
receive a set of accelerator-decoded JPEG data blocks from the decoder accelerator via the decoder bus interface;
dequantize the set of accelerator-decoded JPEG data blocks that were previously decoded by the decoder accelerator using the one or more quantization tables to generate a set of dequantized JPEG data blocks;
perform inverse discrete cosine transform on the set of dequantized JPEG data blocks that were previously decoded by the decoder accelerator to generate a set of spatial JPEG data blocks; and
perform color conversion on the set of spatial JPEG data blocks to generate image data from the JPEG file, and
wherein the decoder accelerator is operable to:
store the plurality of Huffman code tables provided from the processor;
receive the encoded data in the JPEG file from the processor;
generate the accelerator-decoded JPEG data blocks using the Huffman code tables; and
transmit the accelerator-decoded JPEG data blocks to the processor.

### Claim 2 (depends on 1)

The computing system of claim 1, wherein the processor is operable to perform the inverse discrete cosine transform on the set of dequantized JPEG data blocks in parallel with the decoder accelerator decoding another set of JPEG data blocks.

### Claim 3 (depends on 1)

The computing system of claim 1, wherein the decoder bus interface is a packetized interface supporting a plurality of packet types including a starting packet type to initialize the decoder accelerator for a new JPEG file, a load table packet type to load the plurality of Huffman code tables into the decoder accelerator, and a send bitstream data packet type to transmit the encoded data in the JPEG file to the decoder accelerator, wherein each packet being transmitted from the processor to the decoder accelerator includes a packet type identifier to identify the packet type of the packet.

### Claim 4 (depends on 3)

The computing system of claim 3, wherein each load table packet is transmitted with a table identifier to indicate whether the corresponding load table packet is loading an AC luminance Huffman code table, a DC luminance Huffman code table, an AC chrominance Huffman code table, or a DC chrominance Huffman code table.

### Claim 5 (depends on 4)

The computing system of claim 4, wherein the table identifier indicates whether a code table corresponding to a load table packet is associated with luminance or chrominance.

### Claim 6 (depends on 1)

The computing system of claim 1, wherein the processor is operable to fuse the accelerator-decoded JPEG data blocks from the decoder accelerator to match a data width of single instruction multiple data (SIMD) instructions of the processor.

### Claim 7

A hardware decoder accelerator comprising:
a decoder bus interface operable to communicate with a processor; and
decoder acceleration circuitry coupled to the decoder bus interface, wherein the decoder acceleration circuitry is operable to:
store a plurality of code tables provided from the processor via the decoder bus interface;
receive encoded data of a compressed data object from the processor via the decoder bus interface;
generate accelerator-decoded data blocks using the plurality of code tables; and
transmit the accelerator-decoded data blocks to the processor for post-processing operations, wherein the post-processing operations of the processor include performing dequantization and inverse discrete cosine transformation on the accelerator-decoded data blocks obtained from the hardware decoder accelerator.

### Claim 8 (depends on 7)

The hardware decoder accelerator of claim 7, wherein the decoder acceleration circuitry is operable to generate the accelerator-decoded data blocks while the processor is performing the post-processing operations in parallel on previous accelerator-decoded data blocks provided from the hardware decoder accelerator.

### Claim 9 (depends on 7)

The hardware decoder accelerator of claim 7, wherein the decode bus interface is a packetized interface supporting a plurality of packet types.

### Claim 10 (depends on 9)

The hardware decoder accelerator of claim 9, wherein the plurality of packet types includes a starting packet type to identify a start packet from the processor to initialize the hardware decoder accelerator, wherein the start packet includes information indicating a number of packets being used to transmit the compressed data object.

### Claim 11 (depends on 9)

The hardware decoder accelerator of claim 9, wherein the plurality of packet types includes a load table packet type from the processor to load the plurality of code tables into the hardware decoder accelerator.

### Claim 12 (depends on 9)

The hardware decoder accelerator of claim 9, wherein the plurality of packet types includes a send bitstream data packet type from the processor to transfer the encoded data to the hardware decoder accelerator.

### Claim 13 (depends on 7)

The hardware decoder accelerator of claim 7, wherein the decoder acceleration circuitry is operable to:
receive a plurality of load table packets, wherein each load table packet includes a table identifier to indicate which of the plurality of code tables that the load table packet corresponds to.

### Claim 14 (depends on 13)

The hardware decoder accelerator of claim 13, wherein the table identifier indicates whether a code table corresponding to a load table packet is associated with an AC component or a DC component.

### Claim 15 (depends on 13)

The hardware decoder accelerator of claim 13, wherein each load table packet includes a table segment identifier to indicate which portion of code data of a corresponding code table is being provided in the load table packet.

### Claim 16 (depends on 13)

The hardware decoder accelerator of claim 13, wherein the plurality of code tables includes a code table having code data that includes a lookahead table associated with the code table.

### Claim 17 (depends on 13)

The hardware decoder accelerator of claim 13, wherein the plurality of code tables includes a code table having code data that includes a set of maximum values associated with the code table, wherein each of the set of maximum values corresponds to a maximum value for a different code length.

### Claim 18 (depends on 8)

The hardware decoder accelerator of claim 8, wherein the post-processing operations being performed in parallel include an upsampling operation.

### Claim 19 (depends on 8)

The hardware decoder accelerator of claim 8, wherein the post-processing operations being performed in parallel include a color space conversion operation.

### Claim 20 (depends on 7)

The hardware decoder accelerator of claim 7, wherein the encoded data is from a JPEG image file.