Signal and power integrated analog analysis system and method for full chip system

A simulation system, comprising:

• a memory module configured to store a plurality of commands;
• a processor configured to execute the plurality of commands stored in the memory module, to perform a simulation analysis program on a full chip system, wherein the full chip system comprises a package structure, a printed circuit board, and a system on a chip (SoC), and the simulation analysis program comprises executing the following steps:
• generating a plurality of signal channel models corresponding to a plurality of input/output power domains, respectively, based on design layouts of the package structure and the printed circuit board;
• generating a system power transmission model based on the design layouts of the package structure and the printed circuit board, and distributions of power supply nodes on a layout of the SoC;
• establishing a plurality of interface connection circuit models for the plurality of input/output power domains, respectively;
• wherein each of the plurality of interface connection circuit models comprises a transmitter, a signal channel model corresponding to the transmitter, a receiver, a current measurement point and a voltage measurement point, in each of the plurality of interface connection circuit models, two ends of the signal channel model are connected to the transmitter and the receiver, respectively, and the transmitter comprises a data input terminal, a clock terminal, and an input/output power terminal, the current measurement point is disposed on the input/output power terminal, the voltage measurement point is disposed on a connection part between the signal channel model and the receiver;
• generating a second current time-domain model based on a response of a first current time-domain model corresponding to each of the plurality of interface connection circuit models at the current measurement point when the data input terminal receives random data;
• when the data input terminal of the first current time-domain model corresponding to each of the plurality of interface connection circuit models receives the random data,
• comparing a current data bit and a previous data bit in the random data, to obtain an interface data change corresponding to each of the plurality of first current time-domain models;
• generating the second current time-domain model corresponding to each of the plurality of first current time-domain models, based on the first current time-domain model corresponding to each of the plurality of interface connection circuit models, and the current step response of the current measurement point of each of the plurality of first current time-domain models and the interface data change corresponding to each of the plurality of first current time-domain models;
• wherein when the current data bit is the same as the previous data bit, a current of the current measurement point of the first current time-domain model is zero;
• and
• generating a third current time-domain model based on a current change at each of the power supply nodes of a digital circuit corresponding to a digital power domain;
• simulating a current step response of the current measurement point in each of the plurality of interface connection circuit models, by a simulation program with integrated circuit emphasis (SPICE), to generate a first current time-domain model corresponding to the each of the plurality of interface connection circuit models;
• and
• simulating a voltage step response of the voltage measurement point when the clock terminal of each of the plurality of interface connection circuit models receives an ideal signal, by the SPICE, to generate a first voltage time-domain model corresponding to the each of the plurality of interface connection circuit models;
• connecting to the system power transmission model, each of the plurality of second current time-domain models and each of the plurality of third current time-domain models, to generate a complete power transmission model, and obtain a power noise generated after the complete power transmission model obtains a supply current;
• recording a clock signal outputted by a phase lock loop, wherein the phase lock loop is connected to each of the plurality of interface connection circuit models;
• simulating a sensitivity of each of the plurality of interface connection circuit models to power by the SPICE, based on transmission of the clock signal outputted from the phase lock loop, to obtain jitter time-domain information of each of the plurality of interface connection circuit models under the power noise;
• and
• generating a system waveform corresponding to each of the plurality of interface connection circuit models, based on the jitter time-domain information of each of the plurality of interface connection circuit models under the power noise, the first voltage time-domain model corresponding to each of the plurality of interface connection circuit models, and data transmission in each of the plurality of interface connection circuit models, to obtain an eye diagram and a time-domain jitter distribution corresponding to each of the plurality of interface connection circuit models.