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US 12,619,557 B1Granted
Signal processing and transmission in electronic circuits
AssigneeAuradine, Inc.
InventorsDavid Carlson, Shahriar Ilislamloo
Life of this patent
Estimating the term…
Abstract
An integrated circuit (IC) chip receives an input signal on a bus connecting a number of IC chips in series. The IC chip is one of the number of IC chips. The IC chip determines whether the bus is in a busy state or an idle state. If the IC chip determines that the bus is in the idle state, the IC chip blocks communication from upstream chips on the bus, and transmit data on the bus. If the IC chip determines that the bus is in the busy state, the IC chip delays transmitting the data on the bus for a delay period, and transmits its data on the bus if the bus is determined to be in the idle state upon expiry of the delay period.
Claims21
A method, comprising:
- determining, by an integrated circuit (IC) chip of a plurality of IC chips that are connected in series on a bus, availability of data for transmission on the bus;
- in response to determining the availability of the data for transmission on the bus, accessing, by the IC chip, the bus;
- upon accessing the bus, determining, by the IC chip, that the bus is in an idle state;
- in response to determining that the bus is in the idle state:
- blocking, by the IC chip using a signal processing circuit in the IC chip, communication from upstream chips of the plurality of IC chips on the bus, wherein the signal processing circuit is configured to receive a blocking signal and block the communication from the upstream chips based on the blocking signal;
- and
- transmitting, by the IC chip, the data on the bus,
- determining, by the IC chip, availability of additional data for transmission on the bus;
- in response to determining the availability of additional data for transmission on the bus, accessing, by the IC chip, the bus at a second time;
- upon accessing the bus the second time, determining, by the IC chip, that the bus is in a busy state;
- in response to determining that the bus is in the busy state, delaying, by the IC chip, transmitting the additional data on the bus for a known amount of time;
- upon expiry of the known amount of time, accessing, by the IC chip, the bus;
- upon accessing the bus, determining, by the IC chip, that the bus is in an idle state;
- and
- in response to determining that the bus is in the idle state:
- blocking, by the IC chip, communication from upstream chips of the plurality of IC chips on the bus;
- and
- transmitting, by the IC chip, the additional data on the bus.
15 more elements
An electronic circuit, comprising:
- a plurality of integrated circuit (IC) chips that are series connected using a plurality of buses, wherein an IC chip of the plurality of IC chips comprises:
- an input terminal on a bus of the plurality of buses connected to the IC chip, wherein the input terminal is coupled to an output terminal of an upstream neighboring chip of a plurality of IC chips that is series connected to the IC chip using the bus;
- an output terminal on the bus, wherein the output terminal is coupled to an input terminal of a downstream neighboring chip of the plurality of IC chips that is series connected to the IC chip using the bus, wherein the plurality of IC chips comprise the IC chip, the upstream neighboring chip, and the downstream neighboring chip;
- a controller circuit to manage data transmission on the bus, wherein the controller circuit is configured to:
- determine availability of data for transmission on the bus;
- in response to determining the availability of the data for transmission on the bus, access the bus;
- upon accessing the bus, determine that the bus is in an idle state;
- in response to determining that the bus is in the idle state:
- block, using a signal processing circuit in the IC chip, communication from upstream chips of the plurality of IC chips on the bus, wherein the signal processing circuit is configured to receive a blocking signal and block the communication from the upstream chips based on the blocking signal;
- and
- transmit the data on the bus;
- determine availability of additional data for transmission on the bus;
- in response to determining the availability of additional data for transmission on the bus, access the bus at a second time;
- upon accessing the bus the second time, determine that the bus is in a busy state;
- in response to determining that the bus is in the busy state, delay transmitting the additional data on the bus for a known amount of time;
- upon expiry of the known amount of time, access the bus;
- upon accessing the bus, determine that the bus is in an idle state;
- and
- in response to determining that the bus is in the idle state:
- block communication from upstream chips of the plurality of IC chips on the bus;
- and
- transmit the additional data on the bus.
19 more elements
An integrated circuit (IC) chip, comprising:
- an input terminal on a bus connected to the IC chip, wherein the input terminal is coupled to an output terminal of an upstream neighboring chip of a plurality of IC chips that is series connected to the IC chip using the bus;
- an output terminal on the bus, wherein the output terminal is coupled to an input terminal of a downstream neighboring chip of the plurality of IC chips that is series connected to the IC chip using the bus,
- wherein the plurality of IC chips comprise the IC chip, the upstream neighboring chip, and the downstream neighboring chip;
- a controller circuit to manage data transmission on the bus, wherein the controller circuit is configured to:
- determine availability of data for transmission on the bus;
- in response to determining the availability of the data for transmission on the bus, access the bus;
- upon accessing the bus, determine that the bus is in an idle state;
- in response to determining that the bus is in the idle state:
- block, using a signal processing signal processing circuit in the IC chip, communication from upstream chips of the plurality of IC chips on the bus, wherein the signal processing circuit is configured to receive a blocking signal and block the communication from the upstream chips based on the blocking signal;
- and
- transmit the data on the bus;
- determine availability of additional data for transmission on the bus;
- in response to determining the availability of additional data for transmission on the bus, access the bus at a second time;
- upon accessing the bus the second time, determine that the bus is in a busy state;
- in response to determining that the bus is in the busy state, delay transmitting the additional data on the bus for a known amount of time;
- upon expiry of the known amount of time, access the bus;
- upon accessing the bus, determine that the bus is in an idle state;
- and
- in response to determining that the bus is in the idle state:
- block communication from upstream chips of the plurality of IC chips on the bus;
- and
- transmit the additional data on the bus.
19 more elements
Dependencies are inferred from the claim text.