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US 12,619,544 B2Granted
Differential approach for indirect memory prefetcher training
AssigneeQUALCOMM Incorporated
InventorsDamian Maiorano, Tanvir Manhotra, Sabine Francis
Life of this patent
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Abstract
Certain aspects of the present disclosure provide techniques and apparatus that may be used to efficiently train address generation components of an indirect memory prefetcher (IMP). In some cases, logical shift operators and comparators may be used to determine an unknown size and base address used to generate a prefetch address.
Claims20
An apparatus for computing an address for an indirect memory prefetch address, comprising:
- circuitry configured to compute a first parameter that represents a difference between a first address of a first entry of a data array and a second address of a second entry of the data array, wherein the first entry of the data array corresponds to a first index of an array of indices and the second entry of the data array corresponds to a second index of the array of indices;
- circuitry configured to compute a second parameter that represents a difference between the first index and the second index;
- circuitry configured to logically shift the second parameter by different values to generate shifted versions of the second parameter;
- circuitry configured to predict a value of a size parameter used for an indirect memory prefetch, wherein the prediction is based on comparisons of the shifted versions of the second parameter by different amounts to find a match between the first parameter and a shifted version of the second parameter;
- circuitry configured to compute a base address for the indirect memory prefetch based on the predicted value of the size parameter, the first parameter, and the second parameter;
- and
- circuitry configured to compute a prefetch address for the indirect memory prefetch based on the computed base address and the predicted value of the size parameter.
4 more elements
A method for computing an address for an indirect memory prefetch address, comprising:
- computing a first parameter that represents a difference between a first address of a first entry of a data array and a second address of a second entry of the data array, wherein the first entry of the data array corresponds to a first index of an array of indices and the second entry of the data array corresponds to a second index of the array of indices;
- computing a second parameter that represents a difference between the first index and the second index;
- logically shifting the second parameter by different values to generate shifted versions of the second parameter;
- predicting a value of a size parameter used for an indirect memory prefetch, wherein the prediction is based on comparisons of the shifted versions of the second parameter by different amounts to find a match between the first parameter and a shifted version of the second parameter;
- computing a base address for the indirect memory prefetch based on the predicted value of the size parameter, the first parameter, and the second parameter;
- and
- computing an address for the indirect memory prefetch based on the computed base address and the predicted value of the size parameter.
4 more elements
An apparatus, comprising:
- means for computing a first parameter that represents a difference between a first address of a first entry of a data array and a second address of a second entry of the data array, wherein the first entry of the data array corresponds to a first index of an array of indices and the second entry of the data array corresponds to a second index of the array of indices;
- means for computing a second parameter that represents a difference between the first index and the second index;
- means for logically shifting the second parameter by different values to generate shifted versions of the second parameter;
- means for predicting a value of a size parameter used for an indirect memory prefetch, wherein the prediction is based on comparisons of the shifted versions of the second parameter by different amounts to find a match between the first parameter and a shifted version of the second parameter;
- means for computing a base address for the indirect memory prefetch based on the predicted value of the size parameter, the first parameter, and the second parameter;
- and
- means for computing an address for the indirect memory prefetch based on the computed base address and the predicted value of the size parameter.
4 more elements
Dependencies are inferred from the claim text.