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US 12,619,541 B2Granted
Concurrent page cache resource access in a multi-plane memory device
AssigneeMicron Technology, Inc.
InventorsSundararajan Sankaranarayanan, Eric N. Lee
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Abstract
A memory device includes a first memory array, a second memory array, and a page cache circuit coupled to the first memory array and the second memory array. The page cache circuit includes at least one set of concurrent resources and at least one shared resource, wherein the at least one set of concurrent resources are asynchronously and concurrently accessible by the first memory array and the second memory array, and wherein the at least one shared resource is accessible in a time-multiplexed fashion by the first memory array and the second memory array.
Claims20
A memory device comprising:
- a first memory array;
- a second memory array;
- and
- a page cache circuit disposed within the memory device and comprising bitline bias circuitry, at least one sense amplifier, and a plurality of registers, wherein the page cache circuit is directly coupled to the first memory array and the second memory array to temporarily store data being read from or written to the first memory array and the second memory array, wherein the page cache circuit comprises at least one set of concurrent resources and at least one shared resource, wherein the at least one set of concurrent resources are concurrently accessible by the first memory array and the second memory array to perform either a same type or different types of memory access operations respectively, wherein the at least one shared resource comprises a cache register and one or more data registers disposed within the page cache circuit, and wherein the cache register and the one or more data registers are accessible in a time-multiplexed fashion by the first memory array and the second memory array such that the cache register and the one or more data registers perform operations on the first memory array and the second memory array successively in time.
1 more element
A method comprising:
- receiving, at a memory device, requests to perform respective memory access operations on a first memory array and a second memory array of the memory device;
- performing at least a portion of the respective memory access operations concurrently using a set of concurrent resources of a page cache circuit disposed within the memory device and directly coupled to the first memory array and the second memory array, wherein the page cache circuit temporarily stores data being read from or written to the first memory array and the second memory array;
- and
- performing at least a portion of the respective memory access operations in a time-multiplexed fashion using at least one shared resource of the page cache circuit, wherein the at least one shared resource comprises a cache register and one or more data registers disposed within the page cache circuit, and wherein performing at least the portion of the respective memory access operations in the time-multiplexed fashion comprises performing operations on the first memory array and the second memory array successively in time using the cache register and the one or more data registers.
1 more element
A memory device comprising:
- a plurality of memory arrays;
- and
- a page cache circuit disposed within the memory device and comprising bitline bias circuitry, at least one sense amplifier, and a plurality of registers, wherein the page cache circuit is directly coupled to the plurality of memory arrays to temporarily store data being read from or written to the plurality of memory arrays, wherein the page cache circuit comprises at least one set of concurrent resources configured to perform operations on the plurality of memory arrays concurrently, and at least one shared resource configured to perform operations on the plurality of memory arrays successively in time, the at least one shared resource comprising a cache register and one or more data registers disposed within the page cache circuit, wherein the cache register and the one or more data registers are accessible in a time-multiplexed fashion by the plurality of memory arrays such that the cache register and the one or more data registers perform operations on the plurality of memory arrays successively in time.
Dependencies are inferred from the claim text.