Memory and operating method thereof

A method for operating a memory, the memory comprising a memory array and an access interface for external access to the memory array, the access interface comprising at least one data/address multiplexing line for transmitting data and address, and the access interface adopting a SPI protocol;

• the method comprising:
• starting a specified column access mode, in which the memory array can be continuously read or written in response to receiving multiple access addresses, wherein the multiple access addresses have a same row address and multiple column addresses;
• receiving a row address and at least one column address via the data/address multiplexing line;
• outputting data read in response to the received access address via the data/address multiplexing line in the case where the specified column access mode indicates a read operation, or receiving data to be written in response to the received access address via the data/address multiplexing line in the case where the specified column access mode indicates a write operation;
• and
• ending the column access mode by receiving an invalid chip enable signal;
• before ending the column access mode, and after outputting or receiving data read or to be written in response to any previously received access address via the data/address multiplexing line, receiving one or more new column addresses via the data/address multiplexing line, and performing the read operation or write operation in response to the received new column addresses, wherein the total number of received column addresses is not limited;
• wherein,
• the timing for receiving the new column addresses is determined by a preset data amount for the previous read/write operation or a number of clock cycles required for the previous read/write operation, or determined by implementing handshake with a host via another transmission line included in the access interface.

A method for operating a memory, the memory comprising a memory array and an access interface for external access to the memory array, the access interface comprising at least one data/address multiplexing line for transmitting data and address, and the access interface adopts a SPI protocol;

• the method comprises:
• starting a specified row access mode, in which the memory array can be continuously read or written in response to receiving multiple access addresses, wherein the multiple access addresses have multiple row addresses and multiple column addresses;
• receiving at least two access addresses via the data/address multiplexing line, wherein each of the access addresses includes a row address and a column address;
• outputting data read in response to the received access addresses via the data/address multiplexing line in the case where the specified row access mode indicates a read operation, or receiving data to be written in response to the received access addresses via the data/address multiplexing line in the case where the specified row access mode indicates a write operation;
• and
• ending the row access mode by receiving an invalid chip enable signal;
• the amount of data read or to be written in response to each access address is equal to a burst length*8 bits, wherein the burst length is preset in a mode register;
• and/or
• the specified row access mode is started by receiving a predetermined command via the data/address multiplexing line, or started by a preset mode register.