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US 12,619,434 B2Granted
Programmable fabric-based instruction set architecture for a processor
AssigneeAltera Corporation
InventorsDheeraj Subbareddy, Anshuman Thakur, Ankireddy Nalamalpu, MD Altaf Hossain
Life of this patent
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Abstract
A semiconductor device may include a programmable fabric and a processor. The processor may utilize one or more extension architectures. At least one of these extension architectures may be used to integrate and/or embed the programmable fabric into the processor as part of the processor. Specifically, a buffer of the extension architecture may be used to load data to and store data from the programmable fabric.
Claims37
An integrated circuit device comprising:
- a processor comprising:
- a register to store information that is processed in the processor;
- a decode unit to decode instructions for the processor;
- extension architecture coupled to the decode unit that is configured to receive the instructions from the decode unit, wherein the extension architecture comprises:
- a first computation grid comprising a grid of fused-multiply-add circuits tuned to a first format of data;
- a second computation grid comprising a programmable fabric that receives data in a second format of data different than the first format and pre-loads multiple configurations for multiple extension architectures upon boot of the processor;
- and
- control circuitry to receive the decoded instructions as a command, select the first computation grid or the second computation grid, and selectively transmit the command to the first computation grid or the second computation grid, wherein the selection of the first computation grid or the second computation grid is based on the command;
- and
- an execution unit coupled with the decode unit, wherein the execution unit, in response to the instructions, performs operations comprising:
- receiving a microcode update with a configuration bitstream carrying at least one configuration of the multiple configurations that when loaded into the programmable fabric, configures the programmable fabric to perform one or more functions using the at least one configuration;
- validating the microcode update by matching the configuration bitstream to a processor identification (CPUID) corresponding to the processor;
- and
- storing the configuration bitstream to the programmable fabric.
11 more elements
A semiconductor device, comprising:
- a first computation grid comprising a programmable fabric;
- and
- a processor comprising:
- a plurality of cores;
- and
- extension architecture that is configured to receive a command from a core of the plurality of cores, wherein the extension architecture comprises:
- a data buffer;
- a second computation grid comprising a grid of fused-multiply-add circuits tuned to a first format of data, wherein the programmable fabric receives data in a second format of data different than the first format and pre-loads multiple configurations for multiple extension architectures upon boot of the processor;
- and
- control circuitry to receive the command, select the first computation grid or the second computation grid, and selectively transmit the command to the first computation grid or the second computation grid, wherein the selection of the first computation grid or the second computation grid is based on a type of the command;
- and
- a decode unit to decode instructions for the processor;
- an execution unit coupled with the decode unit, wherein the execution unit, in response to the instructions, performs operations comprising:
- receiving a microcode update with a configuration bitstream carrying at least one configuration of the multiple configurations that when loaded into the programmable fabric, configures the programmable fabric to perform one or more functions using the at least one configuration;
- validating the microcode update by matching the configuration bitstream to a processor identification (CPUID) corresponding to the processor;
- and
- storing the configuration bitstream to the programmable fabric.
14 more elements
A method comprising:
- loading multiple configurations for multiple extension architectures upon boot of a processor into a programmable fabric;
- receiving, at control circuitry of extension architecture of the processor, a command from a core of the processor;
- based on a command type of the command, identifying a first computation grid or a second computation grid as a target of the command;
- based on identification of the first computation grid as the target of the command, transmitting the command to the programmable fabric of the first computation grid, wherein the command pertains to data in a first format that is different than a second format to which a second computation grid of the processor is tuned;
- receiving results for the command from the programmable fabric after conversion to the second format;
- transmitting the results to the core;
- receiving, at an execution unit of the processor, a microcode update with a configuration bitstream carrying at least one configuration of the multiple configurations that when loaded into the programmable fabric, configures the programmable fabric to perform one or more functions using the at least one configuration;
- validating, by the processor, the microcode update by matching the configuration bitstream to a processor identification (CPUID) corresponding to the processor;
- and
- storing, by the processor, the configuration bitstream to the programmable fabric.
7 more elements
A semiconductor device comprising:
- a programmable fabric;
- and
- a processor comprising:
- extension architecture that embeds the programmable fabric in the processor and comprises a register used to exchange data between the programmable fabric and the processor, wherein the extension architecture comprises a grid of fused-multiply-add circuits tuned to a first format of data, wherein the programmable fabric receives data in a second format of data different than the first format, and the programmable fabric pre-loads multiple configurations for multiple extension architectures upon boot of the processor;
- a decode unit to decode instructions for the processor and the programmable fabric;
- and
- an execution unit coupled with the decode unit, wherein the execution unit, in response to the instructions, performs operations comprising:
- performing a first task using the programmable fabric when the data is received in the second format;
- generating or receiving an indication to switch to a second task for the processor;
- determining whether the second task utilizes the programmable fabric;
- when the second task does not utilize the programmable fabric, switching to the second task without saving a state of the programmable fabric in response to the indication before switching;
- receiving a microcode update with a configuration bitstream carrying at least one configuration of the multiple configurations that when loaded into the programmable fabric, configures the programmable fabric to perform one or more functions using the at least one configuration;
- validating the microcode update by matching the configuration bitstream to a processor identification (CPUID) corresponding to the processor;
- and
- storing the configuration bitstream to the programmable fabric.
12 more elements
Dependencies are inferred from the claim text.