Method and apparatus for computer operation improvement by flattening multi-level data structures to optimize pointer chase

An apparatus for compiler optimization, the apparatus comprising:

• a processor;
• and
• a memory having machine executable instructions stored thereon, the instructions when executed by the processor configure the apparatus to:
• determine, in an intermediate representation (IR) of a computer program, one or more optimization candidates, each optimization candidate comprising a chain of two or more pointers ultimately referencing information stored in memory;
• generate, for the one or more optimization candidates, a replacement data structure ultimately indicative of the information stored in memory;
• for the one or more optimization candidates, analyze memory location modification and reference (mod/ref) effects to determine feasibility of replacing the chain with a flattened data structure for the one or more optimization candidates;
• for the one or more optimization candidates determined to be feasible, determine shapes for one or more caches to be associated with one or more optimization candidates determined to be feasible and allocating the one or more caches for storing the replacement data structure ultimately indicative of the information stored in memory;
• and
• generate computer code to write to, read from, or both write to and read from the one or more caches.

A computer program product comprising a non-transitory computer readable medium storing computer executable instructions thereon that when executed by a computer perform the method for compiler optimization, the method comprising:

• determining, in an intermediate representation (IR) of a computer program, one or more optimization candidates, each optimization candidate comprising a chain of two or more pointers ultimately referencing information stored in memory;
• generating, for the one or more optimization candidates, a replacement data structure ultimately indicative of the information stored in memory;
• for the one or more optimization candidates, analyzing memory location modification and reference (mod/ref) effects to determine feasibility of replacing the chain with a flattened data structure for the one or more optimization candidates;
• for the one or more optimization candidates determined to be feasible, determining shapes for one or more caches to be associated with one or more optimization candidates determined to be feasible and allocating the one or more caches for storing the replacement data structure ultimately indicative of the information stored in memory;
• and
• generating computer code to write to, read from, or both write to and read from the one or more caches.