Method of performing hardware efficient unbiased rounding of a number

A method of processing an input value to a processing system, said input value comprising a number representing data, the method comprising:

• receiving, at a first adder implemented in hardware logic, the number in a binary format with a bit length of m bits, having a first portion with bit length of ‘a’ bits and second portion with bit-length of ‘b’ bits, wherein the first portion comprises bits of the number above a rounding point and the second portion comprises bits of the number after the rounding point;
• performing a hardware efficient unbiased rounding of the number by:
• adding, by the first adder, a first amount to the number to obtain a first value;
• determining if the bit above the rounding point for a controlling value is ‘0’ bit or a ‘1’ bit, wherein the controlling value is either the received number in the binary format or the first value;
• if the bit above the rounding point for the controlling value is a ‘0’ bit, adding, by a second adder implemented in hardware logic, a second amount to ‘b+1’ LSBs of the first value to obtain a second value and truncating the last b bits of the second value by a shifter implemented in hardware logic;
• or
• if the bit above the rounding point for the controlling value is a ‘1’ bit, truncating the last b bits of the first value by said shifter;
• wherein the first amount and the second amount to be added are determined based on the number of ‘b’ bits of the second portion and wherein the first value and the second value are represented in the same binary format as the received number;
• and
• outputting the truncated value from the shifter to the processing system to facilitate processing of said number by the processing system.