Simplified clocking and input/output timing using single data rate link for multiple system-on-chip device

An electronic device, comprising:

• a first system-on-chip (SOC);
• a second SOC;
• and
• a SoundWire bridge connecting the first SOC to the second SOC, wherein the SoundWire bridge has a single clock line, wherein:
• the first SOC is configured to generate peripheral data and a single data rate (SDR) clock signal to transport to the second SOC,
• the first SOC is configured to drive the peripheral data onto a data bus during one or more drive phases associated with the SDR clock signal, and
• the second SOC is configured to sample the peripheral data from the data bus during one or more bus keeper phases associated with the SDR clock signal.

An apparatus, comprising:

• means for generating peripheral data and a single data rate (SDR) clock signal to transport over a SoundWire bridge having a single clock line;
• and
• means for transporting the peripheral data over the SoundWire bridge according to the SDR clock signal carried on the single clock line, wherein the means for transporting the peripheral data over the SoundWire bridge includes:
• means for driving the peripheral data onto a data bus during one or more drive phases associated with the SDR clock signal;
• and
• means for sampling the peripheral data from the data bus during one or more bus keeper phases associated with the SDR clock signal.