US 12,616,073 B2Granted

3D semiconductor device and structure with metal layers

AssigneeMonolithic 3D Inc.

InventorsZvi Or-Bach, Brian Cronquist

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Abstract

A 3D semiconductor device including: a first level with first transistors, a single-crystal layer and at least one metal layer which includes interconnects between the first transistors forming first control circuits with a plurality of sense amplifiers; the first metal layer(s) overlaid by a second metal layer which is overlaid by a second level which includes first memory-cells which include second transistors with a metal-gate, overlaid by a third level which includes second memory cells which include third transistors which control the data written to second memory cells; a fourth metal layer overlaying a third metal layer which overlays the third level; where third transistor gate locations are aligned to second transistor gate locations within greater than 0.2 nm error, the first transistors or the second transistors comprise at least two FinFet transistors, and two of the FinFet transistors each have different threshold voltages.

Claims20

Dependent claims

A 3D semiconductor device, the device comprising:

a first level comprising a first single crystal layer, said first level comprising a plurality of first transistors and at least one first metal layer,
wherein said at least one first metal layer comprises interconnects between said first transistors thus comprising formation of first control circuits;
a second metal layer connected to said first metal layer and comprising formation of first control circuits;
a second level overlaying said first level, said second level comprising a plurality of second transistors;
a third level overlaying said second level, said third level comprising a plurality of third transistors;
a plurality of sense amplifiers,
wherein said second level comprises a plurality of first memory cells, said plurality of first memory cells each comprising at least one of said plurality of second transistors,
wherein said third level comprises a plurality of second memory cells, said plurality of second memory cells each comprising at least one of said plurality of third transistors,
wherein at least one of said plurality of second memory cells is at least partially disposed atop of said first control circuits, and
wherein said first control circuits are connected to control data written to at least one of said plurality of second memory cells;
a third metal layer disposed above said third level;
and
a fourth metal layer disposed above said third metal layer,
wherein said plurality of second transistors comprises second transistor gate locations,
wherein said plurality of third transistors comprises third transistor gate locations,
wherein said third transistor gate locations are aligned to said second transistor gate locations with a greater than 0.2 nm alignment error, being formed following two independently aligned lithography steps,
wherein at least one of said second transistors comprises a metal gate, and
wherein said plurality of first transistors or said plurality of second transistors comprise at least two FinFet transistors, and
wherein two of said at least two FinFet transistors each have different threshold voltages (Vt).

16 more elements

A 3D semiconductor device, the device comprising:

a first level comprising a first single crystal layer, said first level comprising a plurality of first transistors and at least one first metal layer,
wherein said at least one first metal layer comprises interconnects between said plurality of first transistors thus comprising formation of first control circuits;
a second metal layer connected to said first metal layer and comprising formation of first control circuits;
a second level overlaying said first level, said second level comprising a plurality of second transistors;
a third level overlaying said second level, said third level comprising a plurality of third transistors;
a plurality of sense amplifiers,
wherein said second level comprises a plurality of first memory cells, said plurality of first memory cells each comprising at least one of said plurality of second transistors,
wherein said third level comprises a plurality of second memory cells, said plurality of second memory cells each comprising at least one of said third transistors,
wherein at least one of said plurality of second memory cells is at least partially disposed atop of said first control circuits, and
wherein said first control circuits are connected to control data written to at least one of said plurality of second memory cells;
a third metal layer disposed above said third level;
a fourth metal layer disposed above said third metal layer,
wherein said plurality of second transistors comprises second transistor gate locations,
wherein said plurality of third transistors comprises third transistor gate locations,
wherein said third transistor gate locations are aligned to said second transistor gate locations with a greater than 0.2 nm alignment error, being formed following two independently aligned lithography steps,
wherein at least one of said plurality of second transistors comprises a metal gate;
and
a plurality of vias disposed through said first single crystal layer.

15 more elements

A 3D semiconductor device, the device comprising:

a first level comprising a first single crystal layer, said first level comprising a plurality of first transistors and at least one first metal layer,
wherein said at least one first metal layer comprises interconnects between said plurality of first transistors thus comprising formation of first control circuits;
a second metal layer connected to said first metal layer and comprising formation of first control circuits;
a second level overlaying said first level, said second level comprising a plurality of second transistors;
a third level overlaying said second level, said third level comprising a plurality of third transistors;
a plurality of sense amplifiers,
wherein said second level comprises a plurality of first memory cells, said plurality of first memory cells each comprising at least one of said plurality of second transistors,
wherein said third level comprises a plurality of second memory cells, said plurality of second memory cells each comprising at least one of said plurality of third transistors,
wherein at least one of said second memory cells is at least partially disposed atop of said first control circuits, and
wherein said first control circuits are connected to control data written to at least one of said plurality of second memory cells;
a third metal layer disposed above said third level;
a fourth metal layer disposed above said third metal layer,
wherein said plurality of second transistors comprises second transistor gate locations,
wherein said plurality of third transistors comprises third transistor gate locations,
wherein said third transistor gate locations are aligned to said second transistor gate locations with a greater than 0.2 nm alignment error, being formed following two independently aligned lithography steps,
wherein at least one of said plurality of second transistors comprises a metal gate;
and
a heat removal path from at least one of said plurality of second transistors to an external surface of said device.

15 more elements

Dependencies are inferred from the claim text.

Facts

Application: 19/245,372Filed 22 Jun 2025 · continuation in part
Priority: 22 Dec 2012
Published: US 2025/0070091 A19 Oct 2025
Granted: 28 Apr 2026
Term ends: Not estimatedThe source records don’t support an estimate.

Classification41 codes

H10W 90/00
Package configurations
H10B 12/20
Dynamic random access memory [DRAM] devices: dRAM devices comprising floating-body transistors, e.g. floating-body cells
H10B 43/20
EEPROM devices comprising charge-trapping gate insulators: characterised by three-dimensional [3D] arrangements, e.g. with cells on different…
H10D 64/027
Forming recessed gates, e.g. by using local oxidation: by etching at gate locations

Family

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US 2015/0069523 A1Published application
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US 12,616,073 B2This patent

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