Three-dimensional fan-out integrated package structure, packaging method thereof, and wireless headset

A method for preparing a three-dimensional fan-out integrated packaging structure, comprising following operation steps:

• providing a support substrate, and forming a separation layer on the support substrate;
• forming a second rewiring layer on the separation layer, wherein the second rewiring layer comprises a second dielectric layer and a second metal wire layer disposed in the second dielectric layer,
• forming a plurality of metal connection pillars on the second rewiring layer and at sides of a first semiconductor chip and second semiconductor chip stacked together, and electrically connected to the second rewiring layer;
• wherein the second semiconductor chip has a first surface and a second surface, and the second surface of the second semiconductor chip is bonded to the second rewiring layer,
• wherein the first semiconductor chip has a first surface and a second surface, wherein the second surface of the first semiconductor chip is stacked on the first surface of the second semiconductor chip with a metal conductive layer in between;
• and wherein the first semiconductor chip is electrically connected to the second semiconductor chip through the metal conductive layer;
• forming a first filler layer in a gap in the metal conductive layer of the stack of the first semiconductor chip and the second semiconductor chip;
• forming a first encapsulating layer on the second rewiring layer, wherein the first encapsulating layer encapsulates the plurality of metal connection pillars, the first semiconductor chip, and the second semiconductor chip;
• forming a first rewiring layer on the first encapsulating layer, wherein the first rewiring layer comprises a first dielectric layer and a first metal wire layer disposed in the first dielectric layer, and electrically connecting the first metal wire layer to the second semiconductor chip and the plurality of metal connection pillars;
• wherein the second rewiring layer is configured to be on the first surface of the second semiconductor chip, wherein the second rewiring layer and the first rewiring layer are parallel and located on opposite sides of the stacked first semiconductor chip and second semiconductor chip;
• forming metal bumps on a surface of the first rewiring layer away from the stacked first semiconductor chip and second semiconductor chip, and electrically connecting the metal bumps to the first metal wire layer,
• providing a carrier, and flipping the three-dimensional fan-out integrated packaging structure upside down on the carrier,
• peeling off the support substrate at the separation layer, to expose a surface of the second rewiring layer away from the stacked first semiconductor chip and second semiconductor chip;
• providing a plurality of functional chips on said exposed surface of the second rewiring layer, and electrically connecting the plurality of functional chips to the second metal wire layer,
• forming a second filler layer in a gap between the plurality of functional chips and the second rewiring layer,
• forming a second encapsulating layer on the surface of the second rewiring layer away from the stacked first semiconductor chip and second semiconductor chip, wherein the second encapsulating layer encapsulates the plurality of functional chips;
• and
• removing the carrier.