Stacked random-access memory devices with refrigeration

An integrated circuit (IC) device comprising:

• a substrate;
• a memory array comprising a plurality of bitcells, the memory array over the substrate;
• and
• a cooling structure formed around the substrate and the memory array, the cooling structure in thermal contact with the memory array, wherein the cooling structure comprises a liquid coolant surrounding at least a portion of the memory array and the substrate.

An integrated circuit (IC) device comprising:

• a first memory layer comprising a first memory array;
• a second memory layer comprising a second memory array, the second memory layer directly over the first memory layer;
• a cooling device;
• a first thermal interface layer in thermal contact with the cooling device and the first memory layer;
• and
• a second thermal interface layer in thermal contact with the cooling device and the second memory layer;
• and
• a via coupling the second thermal interface layer to the cooling device, wherein the via extends through the second memory layer, the first memory layer, and the first thermal interface layer.