Semiconductor package and method of manufacturing the same

A semiconductor package comprising:

• a first semiconductor chip;
• a second semiconductor chip disposed on the first semiconductor chip;
• a connection terminal configured to electrically connect the first semiconductor chip to the second semiconductor chip;
• and
• an underfill material configured to at least partially surround sidewalls of the connection terminal between the first semiconductor chip and the second semiconductor chip,
• wherein the first semiconductor chip comprises:
• a substrate including a first region and a second region at least partially surrounding the first region in a plane defined by a first horizontal direction and a second horizontal direction perpendicular to the first horizontal direction, wherein the substrate has a first surface and a second surface opposed to the first surface;
• a wiring pattern disposed on the first surface of the substrate;
• a first recess formed on the second surface of the substrate and in the second region of the substrate;
• a back side insulating layer disposed on the second surface of the substrate, wherein the back side insulating layer fills an inside of the first recess and comprises a material different from that of the underfill material;
• a through via penetrating through the first region of the substrate and the back side insulating layer, wherein the through via connects to the wiring pattern;
• and
• a second recess formed in the back side insulating layer and on the first recess, wherein the second recess is filled with the underfill material,
• wherein a bottom surface of the second recess is formed higher than the second surface of the substrate.