Interconnect substrate and method of making

A method of making an interconnect substrate, comprising:

• disposing at least one embedded component in a substrate core, wherein:
• the substrate core comprises one or more of:
• a dielectric, encapsulant, ceramic, glass, polymer, mold compound such as epoxy or a thermoset material, at least one tracking identifier, a printed circuit board (PCB) with or without routing, a PCB core, and silicon, and combinations thereof, and
• the at least one embedded component comprising one or more of:
• a semiconductor chip or semiconductor device, a chiplet, an active device or active component, an integrated circuit (IC), a passive device, an integrated passive device (IPD), a deep trench capacitor (DTC), a transformer, a voltage regulator, power management IC (PMIC), a filter, a switch, an amplifier, an interface, a repeater or retimer, a clock, a processor, a controller, an accelerator, a memory, a non-volatile memory (NVM), a cache, a bridge die, and a buffer;
• planarizing a front surface of the substrate core to form a base frontside planar surface and expose at least a portion of the at least one embedded component;
• forming a first frontside conductive layer over the base frontside planar surface, the first frontside conductive layer comprising one or more of traces, vias, lands, lines, pads, and planes configured for coupling to the at least one embedded component;
• disposing a first frontside layer of dielectric over the frontside planar surface, the at least one embedded component, and the first frontside conductive layer;
• rotating the substrate core with the first frontside layer of dielectric unplanarized such that a back surface of the substrate core is configured for processing;
• forming a first backside conductive layer comprising one or more of traces, vias, lands, lines, pads, and planes over the back surface of the substrate core;
• disposing a first backside layer of dielectric over the back surface of the substrate core and over the first backside conductive layer;
• rotating the substrate core with the first backside layer of dielectric unplanarized such that the first frontside layer of dielectric is configured for processing;
• and
• planarizing the first frontside layer of dielectric to expose at least a portion of the first frontside conductive layer to form a first frontside planar surface on the first frontside layer of dielectric.