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US 12,616,034 B2Granted
Carrier structure
AssigneeSiliconware Precision Industries Co., Ltd.
InventorsCheng-Liang Hsu, Wan-Rou Chen, Hsin-Yin Chang, Tsung-Li Lin, Hsiu-Jung Li, Chiu-Lien Li, Fu-Quan Xu, Yi-Wen Liu, Chih-Chieh Sun
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Abstract
A carrier structure is provided, in which at least one positioning area is defined on a chip-placement area of a package substrate, and at least one alignment portion is disposed on the positioning area. Therefore, the precision of manufacturing the alignment portion is improved by disposing the positioning area on the chip-placement area, such that the carrier structure can provide a better alignment mechanism for the chip placement operation.
Claims7
A carrier structure, comprising:
- a package substrate defined with a chip-placement area for a single chip having a plurality of corners, wherein a positioning area is formed at one of the corners of the chip-placement area;
- a first alignment portion with a first pattern;
- and
- a second alignment portion with a second pattern, wherein the first pattern and the second pattern are different, wherein the first alignment portion and the second alignment portion are disposed on the positioning area, wherein the first alignment portion and the second alignment portion are located at two different corners of the positioning area.
1 more element
Dependencies are inferred from the claim text.