Semiconductor package structure

A semiconductor package structure, comprising:

• a substrate;
• and
• at least one chip stack structure, provided on the substrate, wherein the at least one chip stack structure comprises a plurality of first chips vertically stacked, each of the first chips comprises a first conductive plug set, the first conductive plug set comprises a plurality of first conductive plugs, a connection layer is provided between two adjacent first chips, a wire structure is provided in the connection layer, the wire structure is electrically connected to the first conductive plug sets in two first chips adjacent to the wire structure, projections of two first conductive plug sets electrically connected to a same wire structure on the substrate are staggered from each other, and the first conductive plug sets in the plurality of first chips are connected in series through the wire structures to form an inductor structure;
• wherein along a direction in which the plurality of first chips are stacked, the wire structures in the connection layers and the first conductive plug sets in the first chips are sequentially connected to form a spiral structure arranged around a virtual axis, and the virtual axis is perpendicular to a top surface of the substrate;
• wherein each of the first chips further comprises:
• a first interconnect line, provided on a top surface of the first chip, wherein ends of the plurality of first conductive plugs in the first conductive plug set close to the top surface of the first chip are electrically connected in series through the first interconnect line;
• and
• a second interconnect line, provided on a bottom surface of the first chip, wherein ends of the plurality of first conductive plugs in the first conductive plug set close to the bottom surface of the first chip are electrically connected through the second interconnect line.