Stacked random access memory devices with multilayer continuous vias

A memory device comprising:

• a first memory array comprising a first plurality of bitcells;
• a first plurality of peripheral devices coupled to the first memory array, the first plurality of peripheral devices in a first layer of the memory device, and the first memory array in a second layer of the memory device, the second layer over the first layer;
• a first via coupling the first layer to the second layer;
• a second memory array comprising a second plurality of bitcells;
• a second plurality of peripheral devices coupled to the second memory array, the second plurality of peripheral devices in a third layer of the memory device, and the second memory array in a fourth layer of the memory device, the third layer between the second layer and the fourth layer;
• and
• a second via coupling the third layer to a fifth layer, wherein the first layer and the second layer are between the third layer and the fifth layer.