US 12,616,007 B2Granted

Isolation regions within a memory die

AssigneeMicron Technology, Inc.

InventorsRaja Kumar Varma Manthena, Yoshiaki Fukuzumi

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Abstract

Methods, systems, and devices for isolation regions within a memory die are described. During fabrication, memory pillars may be formed through a stack of material in a plurality regions of a memory die. In some cases, a first plurality of trenches extending in a first direction and a second plurality of trenches extending in a second direction may be formed through the stack of material (e.g., interposed between the plurality of regions). Additionally or alternatively, first voids may be formed via the first plurality of trenches, and a dielectric material may be deposited in the first voids and the first plurality of trenches, forming first isolation regions. Then, second voids may be formed via the second plurality of trenches, and a dielectric material may be deposited in the second voids and the second plurality of trenches, forming second isolation regions.

Claims7

Dependent claims

An apparatus, comprising:

a first plane comprising a first plurality of regions, wherein each region of the first plurality of regions comprises a first plurality of pillars;
a second plane comprising a second plurality of regions, wherein each region of the second plurality of regions comprises a second plurality of pillars;
a first isolation region extending in a first direction and bisecting the first plurality of regions of the first plane, wherein the first isolation region comprises a first dimension in a second direction and isolates a first set of the first plurality of regions of the first plane from a second set of the first plurality of regions of the first plane;
and
a second isolation region extending along a first boundary of the second plane and along a second boundary of the second plane, wherein the second isolation region comprises a second dimension in the second direction that corresponds to a same portion of the first isolation region as the first dimension, wherein the second dimension is different than the first dimension, and wherein the second isolation region comprises a first portion extending in the first direction along the first boundary and a second portion extending in the second direction along the second boundary, and wherein the first portion is perpendicular to the second portion.

2 more elements

Dependencies are inferred from the claim text.

Facts

Application: 17/815,915Filed 28 Jul 2022
Published: US 2024/0038577 A11 Feb 2024
Granted: 28 Apr 2026
Term ends: Not estimatedThe source records don’t support an estimate.

Classification10 codes

H10W 10/014
Of isolation regions comprising dielectric materials: using trench refilling with dielectric materials, e.g. shallow trench isolations
H10B 41/10
Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates: characterised by the top-view layout
H10B 41/27
With source and drain on different levels, e.g. with sloping channels: the channels comprising vertical portions, e.g. U-shaped channels
H10B 43/10
EEPROM devices comprising charge-trapping gate insulators: characterised by the top-view layout