Pixel circuit and driving method, display panel and driving method, display device

A display panel, wherein the display panel comprises a pixel circuit, wherein the pixel circuit comprises:

• a driving circuit, connected to a first node, a second node, and a third node, and used for inputting a driving current to the third node through the second node according to a signal at the first node;
• an isolation circuit, connected to the first node, a fourth node, and a first gate driving signal terminal, and used for connecting the first node and the fourth node in response to a signal at the first gate driving signal terminal;
• a compensation circuit, connected to the third node, the fourth node, and a second gate driving signal terminal, and used for connecting the third node and the fourth node in response to a signal at the second gate driving signal terminal;
• a first reset circuit, connected to the fourth node, a first reset signal terminal, and a first initial signal terminal, and used for transmitting a signal at the first initial signal terminal to the fourth node in response to a signal at the first reset signal terminal,
• wherein the display panel comprises:
• a plurality of pixel circuits, arranged in an array along a row direction and a column direction;
• wherein each pixel circuit comprises a light-emission control circuit connected to an enable signal terminal, and the display panel further comprises:
• a plurality of first gate lines, wherein each row of pixel circuits is provided with a respective first gate line, and each first gate line is connected to the first gate driving signal terminal in a respective pixel circuit;
• a plurality of second gate lines, wherein each row of pixel circuits is provided with a respective second gate line, and each second gate line is connected to the second gate driving signal terminal in a respective pixel circuit;
• a plurality of enable signal lines, wherein each row of pixel circuits is provided with a respective enable signal line, and each enable signal line is connected to the enable signal terminal in a respective pixel circuit;
• and
• a plurality of pixel circuit groups, each comprising two adjacent rows of pixel circuits,
• wherein, in a same pixel circuit group, signals at two of the first gate lines are the same in timing, signals at two of the second gate lines are the same in timing, and signals at two of the enable signal lines are the same in timing.