Display substrate, display panel and display apparatus

A display substrate, comprising:

• a base substrate;
• a plurality of pixel circuits on the base substrate;
• and
• a plurality of pixels in an array and on a side of the plurality of pixel circuits away from the base substrate;
• wherein each of the plurality of pixels comprises a first sub-pixel, a second sub-pixel and a third sub-pixel;
• orthographic projections of the first sub-pixel, the second sub-pixel and the third sub-pixel on the base substrate do not overlap with each other;
• the first sub-pixel, the second sub-pixel and the third sub-pixel are electrically connected to corresponding ones of the plurality of pixel circuits in a one-to-one correspondence;
• the first sub-pixel and the second sub-pixel are separated from each other by a first distance in a first direction, and a first via is arranged in the first distance;
• the first sub-pixel and the third sub-pixel are separated from each other by a second distance in the first direction, and another first via is arranged in the second distance;
• and
• the second sub-pixel and the third sub-pixel are separated from each other by a third distance in a second direction perpendicular to the first direction,
• wherein each of the plurality of pixel circuits comprises a driving transistor and an insulating layer, each of the first sub-pixel, the second sub-pixel and the third sub-pixel comprises an anode;
• the driving transistor, the insulating layer and the anode are sequentially arranged away from the base substrate;
• wherein each of the first via, the another first via and a via is formed in the insulating layer, and the first via is configured to connect the anode of the first sub-pixel to a first electrode of the driving transistor in a corresponding one of the plurality of pixel circuits, the another first via is configured to connect the anode of the second sub-pixel to a first electrode of the driving transistor in a corresponding one of plurality of pixel circuits, and the via is configured to connect the anode of the third sub-pixel to a first electrode of the driving transistor in a corresponding one of plurality of pixel circuits,
• wherein the first via, the another first via and the via corresponding to the first sub-pixel, the second sub-pixel and the third sub-pixel in a same pixel are on a same line extending in the second direction,
• wherein each of the plurality of pixel circuits further comprises an auxiliary electrode;
• wherein the insulating layer is further provided with a second via formed for connecting a first conductive layer of the auxiliary electrode to a second conductive layer of the auxiliary electrode;
• and
• an orthographic projection of the second via on the base substrate is between orthographic projections of two pixels adjacent to each other in the second direction on the base substrate, and between orthographic projections of two pixels adjacent to each other in the first direction on the base substrate,
• the auxiliary electrode has a strip shape extending in the second direction;
• an orthographic projection of the auxiliary electrode on the base substrate is between the orthographic projections of the two pixels adjacent to each other in the first direction on the base substrate, and covers the orthographic projection of the second via on the base substrate;
• and
• a length of the auxiliary electrode in the second direction is throughout the two pixels adjacent to each other in the second direction.