Forksheet transistor with advanced cell height scaling

A method of forming a semiconductor structure comprising:

• forming a first dielectric bar between a first set of channel nanosheets of a first nanosheet transistor and a second set of channel nanosheets of a second nanosheet transistor and forming a second dielectric bar between a third set of channel nanosheets of a third nanosheet transistor and a fourth set of channel nanosheets of a fourth nanosheet transistor, the first and the second dielectric bar each having a left sidewall and a right sidewall, the first and the second set of channel nanosheets in direct contact with the left and the right sidewall of the first dielectric bar respectively, the third and the fourth set of channel nanosheets in direct contact with the left and the right sidewall of the second dielectric bar respectively, wherein a lowermost surface of the first dielectric bar has a first depth, a lowermost surface of the second dielectric bar has a second depth, and the first depth is deeper than the second depth relative to a bottom of the first and second sets of channel nanosheets;
• lowering a height of the first dielectric bar in a source/drain (S/D) area of the first and the second nanosheet transistors and lowering a height of the second dielectric bar at a S/D area of the third and the fourth nanosheet transistors;
• forming a first raw S/D region in the S/D area of the first and the second nanosheet transistors and forming a second raw S/D region in the S/D area of the third and the fourth nanosheet transistors;
• and
• performing a first S/D cut to separate the first raw S/D region into a first S/D region of the first nanosheet transistor and a second S/D region of the second nanosheet transistor and performing a second S/D cut to separate the second raw S/D region into a third S/D region of the third nanosheet transistor and a fourth S/D region of the fourth nanosheet transistor.

A semiconductor structure comprising:

• a first and a second dielectric bar each having a left sidewall and a right sidewall;
• a first pair of nanosheet transistors having a first and a second set of channel nanosheets in direct contact with the left and the right sidewall of the first dielectric bar respectively;
• and
• a second pair of nanosheet transistors having a third and a fourth set of channel nanosheets in direct contact with the left and the right sidewall of the second dielectric bar respectively,
• wherein a lowermost surface of the first dielectric bar has a first depth, a lowermost surface of the second dielectric bar has a second depth, and the first depth is deeper than the second depth relative to a bottom of the first and second sets of channel nanosheets.