Semiconductor devices and methods of manufacturing thereof

A method for fabricating semiconductor devices, comprising:

• (a) forming, over a substrate, a first semiconductor channel structure and a second semiconductor channel structure;
• (b) forming, over the substrate, a third semiconductor channel structure and a fourth semiconductor channel structure, wherein the first to fourth semiconductor channel structures all extend along a first direction;
• (c) forming, over the substrate, a first metal gate structure that extends along a second direction perpendicular to the first direction to straddle the first semiconductor channel structure and the second semiconductor channel structure;
• (d) forming, over the substrate, a second metal gate structure that extends along the second direction to straddle the third semiconductor channel structure and the fourth semiconductor channel structure;
• (e) replacing a portion of the first metal gate structure interposed between the first and second semiconductor channel structures with a first gate isolation structure, wherein a width of the first gate isolation structure along the second direction decreases with an increasing depth of the first gate isolation structure toward the substrate;
• and
• (f) replacing a portion of the second metal gate structure interposed between the third and fourth semiconductor channel structures with a second gate isolation structure, wherein a width of the second gate isolation structure along the second direction remains constant with an increasing depth of the second gate isolation structure toward the substrate;
• wherein the method further comprises forming an edge isolation structure by replacing another portion of the first metal gate structure straddling the second semiconductor channel structure, a portion of the first gate isolation structure, and the second semiconductor channel structure with a dielectric material.

A method for fabricating semiconductor devices, comprising:

• (a) forming a first semiconductor channel structure and a second semiconductor channel structure over a first area of a substrate;
• (b) forming a third semiconductor channel structure and a fourth semiconductor channel structure over a second area of the substrate, wherein the first to fourth semiconductor channel structures all extend along a first direction;
• (c) forming a first metal gate structure that extends along a second direction perpendicular to the first direction to straddle the first semiconductor channel structure and the second semiconductor channel structure;
• (d) forming a second metal gate structure that extends along the second direction to straddle the third semiconductor channel structure and the fourth semiconductor channel structure;
• (e) forming a first gate isolation structure by replacing a portion of the first metal gate structure interposed between the first and second semiconductor channel structures, wherein a width of the first gate isolation structure along the second direction decreases with an increasing depth of the first gate isolation structure toward the substrate;
• (f) forming a second gate isolation structure by replacing a portion of the second metal gate structure interposed between the third and fourth semiconductor channel structures, wherein a width of the second gate isolation structure along the second direction remains constant with an increasing depth of the second gate isolation structure toward the substrate;
• and
• (g) forming an edge isolation structure by replacing another portion of the first metal gate structure straddling the second semiconductor channel structure, a portion of the first gate isolation structure, and the second semiconductor channel structure with a dielectric material.