Self-aligned backside contact structure for semiconductor device power delivery

A method comprising:

• forming a field effect transistor including a plurality of source/drain regions and a metal gate structure;
• forming a dielectric layer in contact with a first surface of each of the plurality of source/drain regions;
• forming a bottom dielectric isolation layer in contact with a first surface of the metal gate structure, the bottom dielectric isolation layer being coplanar with the dielectric layer;
• and forming a backside metal contact, the backside metal contact extending through a backside interlevel dielectric and the dielectric layer until an uppermost surface of at least one source/drain region of the plurality of source/drain regions, the backside interlevel dielectric being disposed above the dielectric layer and above the bottom dielectric isolation layer, wherein the backside metal contact electrically connects the at least one source/drain region to a backside interconnect structure disposed above the backside interlevel dielectric;
• wherein the dielectric layer comprises a first dielectric material, wherein the bottom dielectric isolation layer comprises a second dielectric material, wherein an etch rate of the first dielectric material is different from an etch rate of the second dielectric material.