Memory circuitry comprising strings of memory cells

Memory circuitry comprising strings of memory cells, comprising:

• laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers directly above a conductor tier, the insulative tiers and the conductive tiers of the laterally-spaced memory blocks extending from a memory-array region into a stair-step region;
• strings of memory cells comprising operative channel-material strings that extend through the insulative tiers and the conductive tiers in individual of the laterally-spaced memory blocks in the memory-array region, the operative channel-material strings directly electrically coupling with conductor material of the conductor tier;
• and
• the individual laterally-spaced memory blocks comprising an intermediate region between the operative channel-material strings and the stair-step region, a dummy through-array-via (TAV) that extends through the insulative tiers and the conductive tiers in the intermediate region in the individual laterally-spaced memory blocks, the dummy TAV comprising a conductive interconnect structure distinct from a structure of the operative-channel material strings and being directly electrically coupled with the operative channel-material strings in its memory block through the conductor material of the conductor tier that is in its memory block and that extends across an interface of the memory-array region and the intermediate region.

Memory circuitry comprising strings of memory cells, comprising:

• laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers directly above a conductor tier, the insulative tiers and the conductive tiers of the laterally-spaced memory blocks extending from a memory-array region into a stair-step region;
• strings of memory cells comprising operative channel-material strings that extend through the insulative tiers and the conductive tiers in individual of the laterally-spaced memory blocks in the memory-array region, the operative channel-material strings directly electrically coupling with conductor material of the conductor tier;
• and
• the individual laterally-spaced memory blocks comprising an intermediate region between the operative channel-material strings and the stair-step region, a dummy through-array-via (TAV) that extends through the insulative tiers and the conductive tiers in the intermediate region in the individual laterally-spaced memory blocks, the conductor material of the conductor tier spanning between immediately-adjacent of the laterally-spaced memory blocks, the dummy TAV comprising a conductive interconnect structure distinct from a structure of the operative-channel material strings and being directly electrically coupled with the operative channel-material strings in its memory block through some of the conductor material that spans between the immediately-adjacent laterally-spaced memory blocks.

Memory circuitry comprising strings of memory cells, comprising:

• laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers directly above a conductor tier, strings of memory cells comprising operative channel-material strings that extend through the insulative tiers and the conductive tiers, the operative channel-material strings directly electrically coupling with conductor material of the conductor tier;
• a wall that extends through the insulative tiers and the conductive tiers, the wall including an intervening portion that is laterally between two immediately-adjacent of the laterally-spaced memory blocks, the wall including an end portion that joins with the intervening portion and spans across an end of individual of the two immediately-adjacent laterally-spaced memory blocks;
• and
• a dummy through-array-via (TAV) that extends through the insulative tiers and the conductive tiers in the individual two immediately-adjacent memory blocks, the dummy TAV comprising a conductive interconnect structure distinct from a structure of the operative-channel material strings and being directly electrically coupled with the operative channel-material strings in its memory block.