Semiconductor structure and method for forming same
AssigneeSemiconductor Manufacturing North China (Beijing) Corporation
InventorsQiaoming Cai, Lisha Ma
Life of this patent
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Abstract
A semiconductor structure and a method for forming the same are provided. The forming method includes: forming discrete poly gate layers on a base of a first region and a second region, the poly gate layer of the first region including a bottom gate layer and a top gate layer protruding out of the bottom gate layer, the top gate layer and the bottom gate layer defining a groove, and a polish block layer being formed on the sidewall of the groove; forming an interlayer dielectric layer on the base on the side of the poly gate layer; removing the poly gate layer of the second region to form a gate opening; and forming a metal gate layer in the gate opening.
Claims28
A semiconductor structure, comprising:
- a base comprising a first region for forming a first device and a second region for forming a second device, a channel length of the first device being greater than a channel length of the second device;
- a poly gate layer located on the base of the first region, the poly gate layer comprising a bottom gate layer and a top gate layer protruding out of the bottom gate layer, the top gate layer and the bottom gate layer defining a groove;
- a metal gate layer located on the base of the second region;
- a polish block layer located on a sidewall of the groove;
- and
- an interlayer dielectric layer located on the base on a side of the metal gate layer and the poly gate layer.
A method for forming a semiconductor structure, comprising:
- providing a base comprising a first region for forming a first device and a second region for forming a second device, a channel length of the first device being greater than a channel length of the second device;
- forming discrete poly gate layers on the base of the first region and the second region, the poly gate layer of the first region comprising a bottom gate layer and a top gate layer protruding out of the bottom gate layer, the top gate layer and the bottom gate layer defining a groove, and a polish block layer being formed on the sidewall of the groove;
- forming an interlayer dielectric layer on the base on the side of the poly gate layer, the interlayer dielectric layer exposing the top surface of the poly gate layer of the second region;
- removing the poly gate layer of the second region, and forming a gate opening in the interlayer dielectric layer;
- and
- forming a metal gate layer in the gate opening.
Dependencies are inferred from the claim text.