Three-dimensional semiconductor devices

A three-dimensional (3D) semiconductor device comprising:

• a first active region on a substrate, the first active region comprising a lower channel pattern and a pair of lower source/drain patterns on opposing side surfaces of the lower channel pattern, respectively;
• a second active region on the first active region, the second active region comprising an upper channel pattern and a pair of upper source/drain patterns on opposing side surfaces of the upper channel pattern, respectively;
• a dummy channel pattern between the lower channel pattern and the upper channel pattern;
• a pair of liner layers on opposing side surfaces of the dummy channel pattern, respectively;
• and
• a gate electrode on the lower channel pattern, the dummy channel pattern, and the upper channel pattern,
• wherein the gate electrode comprises a lower gate electrode on the lower channel pattern and an upper gate electrode on the upper channel pattern, and
• wherein each of the liner layers vertically overlaps with one of the lower source/drain patterns and one of the upper source/drain patterns.