Stacked FET with low parasitic-capacitance gate
AssigneeInternational Business Machines Corporation
InventorsRuilong Xie, Brent A. Anderson, Junli Wang, Jay William Strane, Albert M. Chu
Life of this patent
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Abstract
A semiconductor device comprises a top field effect transistor (FET) and a bottom FET in a stacked profile. The semiconductor device also comprises a gate. The gate comprises two top-FET gate extensions and two bottom-FET gate extensions. The semiconductor device also comprises an insulator liner. The insulator liner interfaces with the two top-FET gate extensions and two bottom-FET gate extensions. The semiconductor device also comprises a dielectric that interfaces with the insulator liner.
Claims17
A semiconductor device comprising:
- a top field effect transistor (FET);
- a bottom FET, wherein the top FET and bottom FET are in a stacked profile;
- a gate, wherein the gate comprises two top-FET gate sidewall extensions and two bottom-FET gate sidewall extensions, wherein the two top-FET gate sidewall extensions each comprise a gate bump;
- an insulator liner that interfaces with the two top-FET gate sidewall extensions and two bottom-FET gate sidewall extensions;
- and
- a dielectric that interfaces with the insulator liner.
A semiconductor device comprising:
- a top field effect transistor (FET), wherein the top FET comprises a first sidewall gate extension and a second sidewall gate extension, wherein the first sidewall gate extension and the second sidewall gate extension each comprise a gate bump;
- and
- a bottom FET, wherein the bottom FET comprises a third sidewall gate extension and a fourth sidewall gate extension and wherein the top FET and bottom FET are in a stacked profile;
- wherein the first, second, third, and fourth sidewall gate extensions are of equal thickness.
A semiconductor device comprising:
- a top field effect transistor (FET), wherein the top FET comprises a first sidewall gate extension and a second sidewall gate extension;
- a bottom FET, wherein the bottom FET comprises a third sidewall gate extension and a fourth sidewall gate extension and wherein the top FET and bottom FET are in a stacked profile;
- an upper gate extension that connects to the first and second sidewall gate extension, wherein the upper gate extension extends over the bottom FET;
- and
- a first dielectric fill located between the upper gate extension and the bottom FET;
- wherein the first, second, third, and fourth sidewall gate extensions are of equal thickness.
Dependencies are inferred from the claim text.