Semiconductor structure including dielectric wall and spacer layer and method for forming the same

A method for forming a semiconductor structure, comprising:

• forming a plurality of active regions over a substrate;
• forming a plurality of fin spacer layers between the plurality of active regions;
• forming a plurality of dielectric walls nested within the respective fin spacer layers of the plurality of fin spacer layers;
• forming a dummy gate structure over the plurality of active regions, the plurality of fin spacer layers, and the plurality of dielectric walls, wherein interfaces between the dummy gate structure and the plurality of fin spacer layers are higher than interfaces between the dummy gate structure and the plurality of active regions;
• removing the dummy gate structure;
• recessing the plurality of fin spacer layers to expose sidewalls of the plurality of active regions;
• patterning the plurality of active regions to form sets of nanostructures;
• and
• forming a gate stack around the sets of nanostructures.

A semiconductor structure, comprising:

• a first dielectric wall, a first set of nanostructures and a second dielectric wall sequentially arranged in a first horizontal direction;
• a first gate electrode layer wrapping around the first set of nanostructures;
• a source/drain feature adjoining the first set of nanostructures and sandwiched between the first dielectric wall and the second dielectric wall;
• and
• an inner spacer layer interposing between the first gate electrode layer and the source/drain feature and between the first set of nanostructures, wherein in a plan view, a first dimension of the inner spacer layer in the first horizontal direction is greater than a second dimension of the source/drain feature in the first horizontal direction.