Transistor and method for fabricating the same

A method for fabricating a transistor, comprising:

• forming a low-dimensional material layer, a gate dielectric layer, a source, a drain, and a gate above a substrate, wherein the gate dielectric layer is located between the low-dimensional material layer and the gate;
• and
• forming spacers between the source and the gate and between the drain and the gate, respectively, wherein the spacers have fixed charges, wherein the gate, the gate dielectric layer, and the spacers are formed by:
• sequentially forming the low-dimensional material layer, a gate dielectric material layer, and a gate material layer on the substrate;
• patterning the gate material layer to form the gate and expose a part of the gate dielectric material layer where the gate is not located;
• forming a spacer material layer on a top and a sidewall of the gate and the exposed part of the gate dielectric material layer by atomic layer deposition or chemical vapor deposition;
• removing a part of the spacer material layer by dry etching and retaining the spacer material at the sidewall of the gate to form the spacers;
• and
• removing the gate dielectric material layer at a side of each of the spacers away from the gate by etching to form the gate dielectric layer.