Stacked field-effect transistors

A stacked field-effect transistor (FET) comprising:

• a top active region, wherein the width of the top of the top active region is smaller than the width of the bottom of the top active region;
• a top contact in direct contact with a top surface of the top active region;
• a bottom active region located substantially below the top active region;
• and
• a bottom contact in direct contact with a top surface of the bottom active region, the bottom contact being wider at a top end than at a bottom end such that a horizontal distance between the bottom contact and the top active region is substantially identical from a bottom surface of the top active region to the top surface of the top active region.