A manufacturing method of a super junction power device with an adjustable gate resistance structure, comprising steps:
- A:
- preparing a cell structure and an adjustable gate resistance structure of the super junction power device;
- B:
- preparing contact through holes;
- C:
- preparing a metal wire layer;
- and
- D:
- preparing a passivation layer;
- wherein the step A comprises steps:
- S1:
- depositing an intrinsic epitaxial layer on a surface of a silicon substrate by chemical vapor deposition (CVD);
- doping first-type ions on the intrinsic epitaxial layer through an ion implantation process;
- S2:
- depositing a first mask on an upper surface of the intrinsic epitaxial layer, where the first mask is a photoresist or a multi-layer combined structure composed of a photoresist and other insulator masks;
- S3:
- defining column-shaped region patterns on the first mask by photolithography process;
- doping second-type ions on the intrinsic epitaxial layer through the ion implantation process;
- removing the first mask by dry etching and wet etching;
- S4:
- performing the steps S1-S3 repeatedly;
- S5:
- growing a gate oxide layer by thermal oxidation method, and then depositing gate polysilicon by low-pressure CVD, where the gate polysilicon is a first-type in-situ doped gate polysilicon;
- S6:
- depositing a second mask on the gate polysilicon, where the second mask is the photoresist or the multi-layer combined structure composed of the photoresist and other insulator masks;
- defining a gate pattern on the second mask by the photolithography process, forming a gate structure by the dry etching;
- and removing the second mask by the dry etching and the wet etching;
- S7:
- injecting the first-type ions on the upper surface of the intrinsic epitaxial layer by the ion implantation process;
- and activating the first-type ions in the intrinsic epitaxial layer by a thermal process to obtain body regions;
- S8:
- depositing a third mask on an upper surface of a doped intrinsic epitaxial layer, where the third mask is the photoresist or the multi-layer combined structure composed of the photoresist and other insulator masks;
- defining a pattern of source regions on the third mask by the photolithography process;
- injecting the first-type ions on upper surfaces of the body regions by the ion implantation process to obtain a source;
- removing the third mask by the dry etching and the wet etching;
- activating the first-type ions in the source regions by the thermal process;
- and
- S9:
- injecting the second-type ions on the upper surface of the intrinsic epitaxial layer through the ion implantation process to obtain an ohmic contact region, where the ohmic contact region is highly doped, and finally obtaining the cell structure and the adjustable gate resistance structure;
- wherein the gate pattern defines a gate pattern of a cell region metal oxide field effect transistor and adjustable gate resistance structure pattern regions;
- the adjustable gate resistance structure pattern regions are independent patterns of gate resistors with a line width of 5 μm;
- the adjustable gate resistance structure pattern regions are connected in series to three independent gate resistors connected in parallel in a gate loop to make an adjusting range of a resistance of the independent gate resistors to be 1-30Ω.