Display panel with improved mobility of the thin film transistor
AssigneeWuhan China Star Optoelectronics Technology Co., Ltd.
InventorsZhifu Li, Guanghui Liu, Chao Dai, Fei Ai, Dewei Song, Zhuang Li
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Abstract
A display panel is provided by embodiments of the present application, a thin film transistor includes: a first gate electrode including a first side slope, a second side slope oppositely arranged, and a top surface; a first gate insulating layer covering the first gate electrode; a semiconductor layer arranged on the first gate insulating layer, wherein the semiconductor layer includes a first end, a second end, and a channel arranged between the first end and the second end, the second end is at least partially on the top surface, the channel is at least partially located on the first side slope.
Claims16
A display panel, comprising a substrate and a thin film transistor arranged on the substrate, wherein the thin film transistor comprises:
- a first gate arranged on the substrate, wherein the first gate comprises;
- a first side slope and a second side slope oppositely arranged and a top surface arranged between the first side slope and the second side slope;
- a first gate insulating layer covering the substrate, the first side slope, the second side slope, and the top surface;
- a semiconductor layer arranged on the first gate insulating layer, wherein the semiconductor layer comprises a first end, a second end, and a channel located between the first end and the second end, the second end is at least partially located on the top surface, and the channel is at least partially located on the first side slope;
- a first insulating layer arranged on the semiconductor layer;
- a first through hole penetrating the first insulating layer;
- a second through hole penetrating the first insulating layer;
- and
- a source electrode and a drain electrode arranged on the first insulating layer, wherein one of the source electrode and the drain electrode is electrically connected to the first end through the first through hole, and another one of the source electrode and the drain electrode is electrically connected to the second end through the second through hole,
- wherein the thin film transistor further comprises an extension part extending from the first side slope to a side close to the semiconductor layer, a thickness of the extension part is less than a thickness of the first gate electrode, and an orthographic projection of the extension part on the substrate at least partially overlaps an orthographic projection of the channel on the substrate.
A display panel, comprising a substrate and a thin film transistor arranged on the substrate, wherein the thin film transistor comprises:
- a first gate arranged on the substrate, wherein the first gate comprises:
- a first side slope and a second side slope oppositely arranged and a top surface arranged between the first side slope and the second side slope;
- a first gate insulating layer covering the substrate, the first side slope, the second side slope, and the top surface;
- a semiconductor layer arranged on the first gate insulating layer, wherein the semiconductor layer comprises a first end, a second end, and a channel located between the first end and the second end, the second end is at least partially located on the top surface, and the channel is at least partially located on the first side slope;
- a first insulating layer arranged on the semiconductor layer;
- a first through hole penetrating the first insulating layer;
- a second through hole penetrating the first insulating layer;
- a source electrode and a drain electrode arranged on the first insulating layer, wherein one of the source electrode and the drain electrode is electrically connected to the first end through the first through hole, and another one of the source electrode and the drain electrode is electrically connected to the second end through the second through hole;
- a second gate insulating layer arranged between the semiconductor layer and the first insulating layer;
- and
- a second gate electrode arranged between the second gate insulating layer and the first insulating layer, wherein the second gate electrode is arranged corresponding to the channel.
Dependencies are inferred from the claim text.