Transistor with a primary gate wrapping a floating secondary gate

A structure comprising:

• a substrate;
• and
• a transistor on the substrate, wherein the transistor includes:
• a barrier layer;
• a secondary gate on the barrier layer and having opposing sidewalls, opposing end walls and a top surface, wherein the secondary gate includes a P-type III-V semiconductor layer and is floating;
• and
• a primary gate including:
• a gate dielectric layer immediately adjacent to the barrier layer and further extending over and immediately adjacent to the opposing sidewalls, the opposing end walls, and the top surface of the secondary gate;
• and
• a gate conductor layer on the gate dielectric layer,
• wherein the primary gate has first portions on the barrier layer and positioned laterally adjacent to the opposing sidewalls, respectively, of the secondary gate, a second portion on the top surface of the secondary gate, and third portions on the barrier layer and positioned laterally adjacent to the opposing end walls, respectively, of the secondary gate;
• and
• a conformal dielectric layer on a top surface of the gate conductor layer, positioned laterally adjacent to aligned vertical surfaces of the gate conductor layer and the gate dielectric layer, and including a different dielectric material than the gate dielectric layer.

A method comprising:

• providing a substrate;
• and
• forming a transistor on the substrate, wherein the forming of the transistor includes:
• forming a secondary gate on a barrier layer;
• and
• forming a primary gate having first portions on the barrier layer and positioned laterally adjacent to opposing sidewalls, respectively, of the secondary gate, wherein the primary gate includes:
• a gate dielectric layer immediately adjacent to the barrier layer and further extending over and immediately adjacent to the secondary gate;
• and
• a gate conductor layer on the gate dielectric layer;
• and
• forming a conformal dielectric layer on a top surface of the gate conductor layer, positioned laterally adjacent to aligned vertical surfaces of the gate conductor layer and the gate dielectric layer, and including a different dielectric material than the gate dielectric layer.