Multi-gate transistors having deep inner spacers

A semiconductor structure, comprising:

• a substrate;
• a buffer layer disposed on the substrate;
• a first source/drain feature and a second source/drain feature disposed over the buffer layer;
• a plurality of nanostructures extending between the first source/drain feature and the second source/drain feature along a first direction, wherein the plurality of nanostructures are arranged along a second direction perpendicular to the substrate;
• a plurality of inner spacer features interleaving the plurality of nanostructures;
• and
• a gate structure wrapping around each of the plurality of nanostructures,
• wherein the plurality of inner spacer features comprise a bottommost inner spacer feature interfacing a top surface of the buffer layer and upper inner spacer features disposed above the bottommost inner spacer feature,
• wherein a bottommost nanostructure of the plurality of nanostructures is vertically spaced apart from the top surface of the buffer layer by the bottommost inner spacer feature,
• wherein a bottom portion of the gate structure extends continuously through the buffer layer between a bottom surface of the bottommost nanostructure and a top surface of the substrate.

A semiconductor structure, comprising:

• a silicon-on-insulator (SOI) substrate;
• a buffer layer disposed on the SOI substrate;
• a first source/drain feature and a second source/drain feature disposed over the buffer layer;
• a plurality of nanostructures extending between the first source/drain feature and the second source/drain feature along a first direction, wherein the plurality of nanostructures are arranged along a second direction perpendicular to the SOI substrate;
• a plurality of inner spacer features interleaving the plurality of nanostructures;
• and
• a gate structure wrapping around each of the plurality of nanostructures,
• wherein the gate structure extends continuously from along a sidewall of a bottommost one of the plurality of inner spacer features to along a sidewall of the buffer layer,
• wherein a bottom surface of the gate structure is closer to the SOI substrate than a bottom surface of the first source/drain feature.