Semiconductor device and method of manufacturing the same
AssigneeRenesas Electronics Corporation
InventorsMasafumi Hirose, Hitoshi Matsuura
Life of this patent
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Abstract
Techniques are provided for suppressing the accumulation of holes in floating region and improving the switching time of a semiconductor device such as an Insulated Gate Bipolar. The semiconductor device includes a trench gate and a trench emitter formed in a semiconductor substrate, and a floating region of a first conductivity type formed in the semiconductor substrate sandwiched between the trench gate and the trench emitter. The bottom of the floating region is located below the bottom of the trench gate and the trench emitter, and the floating region has a crystal defect region including crystal defects selectively formed at a position near an upper surface of the semiconductor substrate in the floating region.
Claims10
A semiconductor device comprising:
- a semiconductor substrate having a first main surface and a second main surface opposite to the first main surface;
- a first trench and a second trench formed on the semiconductor substrate;
- a first trench emitter formed in the first trench via a first gate insulating film;
- a first trench gate formed in the second trench via a second gate insulating film;
- a floating region of a first conductivity type formed in the semiconductor substrate sandwiched between the first trench emitter and the first trench gate;
- and
- a crystal defect region including crystal defects selectively formed at a position near the first main surface in the floating region, wherein
- in cross-sectional view, the floating region is formed to cover a bottom surface of the first trench and a bottom surface of the second trench, and
- in plan view and cross-sectional view, the crystal defect region separates apart from the first trench and the second trench.
Dependencies are inferred from the claim text.