A semiconductor device, comprising:
- a semiconductor substrate having a first surface and a second surface that are opposite to each other;
- a first semiconductor region of a first conductivity type, the first semiconductor region being provided in the semiconductor substrate;
- a plurality of second semiconductor regions of a second conductivity type, the second semiconductor regions being provided between the first surface of the semiconductor substrate and the first semiconductor region;
- a plurality of third semiconductor regions of the first conductivity type, the third semiconductor regions being selectively provided between the first surface of the semiconductor substrate and the second semiconductor regions;
- a fourth semiconductor region of the second conductivity type, the fourth semiconductor region being provided between the second surface of the semiconductor substrate and the first semiconductor region;
- a plurality of trenches provided in the semiconductor substrate, from the first surface of the semiconductor substrate;
- a plurality of first electrodes respectively provided in the plurality of trenches, each via an insulating film;
- an interlayer insulating film provided on the first surface of the semiconductor substrate, the interlayer insulating film covering the first electrodes and having a plurality of contact holes formed therein;
- a second electrode provided at the first surface of the semiconductor substrate, the second electrode being electrically connected to the second semiconductor regions and the third semiconductor regions via the plurality of contact holes of the interlayer insulating film;
- and
- a third electrode provided on the second surface of the semiconductor substrate, the third electrode being electrically connected to the fourth semiconductor region, wherein
- the trenches are disposed at equal intervals, so as to have a plurality of mesa portions formed therebetween, the trenches including
- a plurality of gate trenches that penetrate through the third semiconductor regions and the second semiconductor regions and reach the first semiconductor region, and
- a plurality of dummy trenches that penetrate through the second semiconductor regions and reach the first semiconductor region;
- the first electrodes include:
- a plurality of gate electrodes respectively provided in the gate trenches, and
- a plurality of dummy electrodes respectively provided in the dummy trenches and electrically connected to the second electrode;
- and
- the plurality of mesa portions includes a plurality of first mesa portions, each of the first mesa portions being provided between two of the gate trenches and including one of the second semiconductor regions that has a floating potential.