Semiconductor device and electronic system the same

A semiconductor device, comprising:

• a lower level layer including a peripheral circuit;
• and
• an upper level layer provided on the lower level layer, the upper level layer including a three-dimensional NAND flash memory cell structure,
• wherein the lower level layer comprises:
• a substrate including an active region;
• a gate insulating pattern on the active region;
• a semiconductor pattern on the gate insulating pattern;
• a metal pattern on the semiconductor pattern;
• and
• a device isolation layer covering a first side surface of the semiconductor pattern, a second side surface of the gate insulating pattern, and a third side surface of the active region and aligning the first side surface, the second side surface, and the third side surface to each other,
• wherein a level of a highest point of a top surface of the device isolation layer is equal to or higher than a level of a top surface of the semiconductor pattern, and
• wherein the metal pattern includes a side portion which is provided on and vertically overlapped with the device isolation layer.

An electronic system, comprising:

• a semiconductor device including an input/output pad electrically connected to peripheral circuits;
• and
• a controller electrically connected to the semiconductor device through the input/output pad and configured to control the semiconductor device,
• wherein the semiconductor device comprises:
• a lower level layer including the peripheral circuits;
• and
• an upper level layer provided on the lower level layer, the upper level layer including a three-dimensional NAND flash memory cell structure,
• wherein the lower level layer comprises:
• a substrate;
• a device isolation layer defining a first active region and a second active region of the substrate;
• a first peripheral transistor and a second peripheral transistor provided on the first active region and the second active region, respectively;
• and
• interconnection lines provided on and electrically connected to the first peripheral transistor and the second peripheral transistor,
• wherein the first peripheral transistor includes a first gate insulating pattern, a first semiconductor pattern, and a first metal pattern, which are sequentially stacked on the first active region,
• wherein the second peripheral transistor includes a second gate insulating pattern, a second semiconductor pattern, and a second metal pattern, which are sequentially stacked on the second active region,
• wherein a thickness of the second gate insulating pattern is larger than a thickness of the first gate insulating pattern,
• wherein the first metal pattern is spaced apart from the device isolation layer,
• wherein the second metal pattern comprises a side portion that is in contact with a top surface of the device isolation layer, and
• wherein the side portion is spaced apart from the second semiconductor pattern with the device isolation layer interposed therebetween.