Semiconductor device

A semiconductor device comprising:

• a first chip including a substrate;
• and
• a second chip bonded to the first chip,
• wherein
• the substrate includes an element region and a first region surrounding the element region,
• the first chip further includes a first electrode pad provided on a surface in contact with the second chip,
• the second chip includes:
• a surface protective layer provided in the element region and a part of the first region;
• a first semiconductor layer at least a part of which is arranged in a second region, the second region being included in the first region and not provided with the surface protective layer;
• a first conductor provided in the first region, surrounding the element region, including one end in a first direction in contact with the first semiconductor layer, and including another end electrically coupled to the substrate;
• a second electrode pad provided on a surface in contact with the first chip and in contact with the first electrode pad;
• a second conductor provided in a layer in which the first conductor is provided in the first region, surrounding the first conductor and the first semiconductor layer, including one end not in contact with the first semiconductor layer, and including another end electrically coupled to the substrate, and
• an interconnect layer provided between the second electrode pad and the first and second conductors in the first direction and to which the first conductor and the second conductor are electrically coupled, and
• the first conductor is coupled to the substrate via the first electrode pad and the second electrode pad.

A semiconductor device comprising:

• a substrate including an element region and a first region surrounding the element region;
• a surface protective layer provided in the element region and a part of the first region;
• a first semiconductor layer at least a part of which is arranged in a second region not provided with the surface protective layer in the first region;
• a first conductor provided in the first region, arranged between the substrate and the first semiconductor layer in a first direction, and including one end in contact with the first semiconductor layer;
• a second conductor provided in a layer in which the first conductor is provided in the first region, surrounding the element region, the first conductor, and the first semiconductor layer, and not in contact with the first semiconductor layer;
• a third conductor provided in a layer in which the first conductor is provided in a third region included in the first region and provided with the surface protective layer, arranged between the element region and the first conductor in a second direction intersecting the first direction, surrounding the element region, and electrically coupled to a first conductive type region provided in the substrate;
• and
• a fourth conductor provided in a layer in which the first conductor and the third conductor are provided in the third region, arranged between the element region and the third conductor in the second direction, surrounding the element region, and electrically coupled to a second conductive type region provided in the substrate,
• wherein
• the first conductor and the second conductor are electrically coupled to the substrate.

A semiconductor device comprising:

• a first chip comprising a substrate;
• and
• a second chip bonded to the first chip on a first surface,
• the first chip and the second chip including an element region and a ring-shaped region surrounding the element region as viewed in a first direction approximately perpendicular to a surface of the substrate, wherein
• the first chip comprises:
• a first electrode pad arranged at the first surface and having a ring shape continuously surrounding the element region within the ring-shaped region as viewed in the first direction, the first electrode pad being electrically coupled to the substrate, and
• the second chip comprises:
• a second electrode pad arranged at the first surface and having a ring shape continuously surrounding the element region within the ring-shaped region as viewed in the first direction, the second electrode pad being in contact with the first electrode pad;
• a first wall structure having a ring shape continuously surrounding the element region within the ring-shaped region as viewed in the first direction, the first wall structure being electrically coupled to the substrate via the second electrode pad and the first electrode pad;
• a first interconnect layer arranged between the second electrode pad and the first wall structure in the first direction and coupled to an end of the first wall structure in the first direction via a first conductor;
• and
• a second interconnect layer arranged between the second electrode pad and the first interconnect layer in the first direction, coupled to the first interconnect layer via a second conductor, and coupled to the second electrode pad via a third conductor, the second interconnect layer having a width larger than a width of the first interconnect layer.